VLDB 2026 Research / reviewers in the wild / expert
Siyi Xu
dblp:303/2715
· DBLP profile ↗
7ranked-venue papers
1as first author
7since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 4 · 4 since 2021Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021Human-computer interaction and ubiquitous computing · 2 · 2 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Late Breaking Results: A Power-Efficient RISC-V Baseband System-on-Chip for Multi-Standard Integrated Sensing and CommunicationsabstractWe present Ishtar, a power-efficient RISC-V baseband system-on-chip (SoC) tailored for multi-standard integrated sensing and communications (ISAC) in low-altitude wireless networks (LAWNs). Ishtar integrates a hierarchical scheduling scheme and a system-level power-gating architecture that dynamically controls power domains to balance performance and energy efficiency. It supports dynamic task scheduling across heterogeneous protocols using a domain-specific, graph-based representation. Implemented in 40 nm technology and running at 300 MHz, Ishtar achieves better normalized efficiency than state-of-the-art SDR SoCs, delivering real-time multi-standard sniffing under stringent power and area constraints. Limin Jiang, Yi Shi 0004, Yihao Shen, Yintao Liu 0001, Siyi Xu, Qingyu Deng, Shan Cao 0001, Zhiyuan Jiang, Sheng Zhou 0001 |
DATE | 5 |
| 2026 | From Noise to Knowledge: Recalibrating Global Decision Boundaries by Generated Prototypes
Dongsu Shen, Siyi Xu |
ICIC (5) | 4 |
| 2025 | A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband ProcessingabstractWireless baseband processing (WBP) is a key element of wireless communications, with a series of signal processing modules to improve data throughput and counter channel fading. Conventional hardware solutions, such as digital signal processors (DSPs) and more recently, graphic processing units (GPUs), provide various degrees of parallelism, yet they both fail to take into account the cyclical and consecutive character of WBP. Furthermore, the large amount of data in WBPs cannot be processed quickly in symmetric multiprocessors (SMPs) due to the unpredictability of memory latency. To address this issue, we propose a hierarchical dataflow-driven architecture to accelerate WBP. A pack-and-ship approach is presented under a non-uniform memory access (NUMA) architecture to allow the subordinate tiles to operate in a bundled access and execute manner. We also propose a multi-level dataflow model and the related scheduling scheme to manage and allocate the heterogeneous hardware resources. Experiment results demonstrate that our prototype achieves 2× and 2.3× speedup in terms of normalized throughput and single-tile clock cycles compared with GPU and DSP counterparts in several critical WBP benchmarks. Additionally, a link-level throughput of 288 Mbps can be achieved with a 45-core configuration. Limin Jiang, Yi Shi 0004, Yintao Liu 0001, Qingyu Deng, Siyi Xu, Yihao Shen, Fangfang Ye, Shan Cao 0001, Zhiyuan Jiang |
ASP-DAC | 5 |
| 2025 | Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)abstractVector processing is crucial for boosting processor performance and efficiency, particularly with data-parallel tasks. The RISC-V ”V” Vector Extension (RVV) enhances algorithm efficiency by supporting vector registers of dynamic sizes and their grouping. Nevertheless, for very long vectors, the static number of RVV vector registers and its power-of-two grouping can lead to performance restrictions. To counteract this limitation, this work introduces Zoozve, a RISC-V vector instruction extension that eliminates the need for strip-mining. Zoozve allows for flexible vector register length and count configurations to boost data computation parallelism. With a data-adaptive register allocation approach, Zoozve permits any register groupings and accurately aligns vector lengths, cutting down register overhead and alleviating performance declines from strip-mining. Additionally, the paper details Zoozve’s compiler and hardware implementations using LLVM and SystemVerilog. Initial results indicate Zoozve yields a minimum 10.10× reduction in dynamic instruction count for fast Fourier transform (FFT), with a mere 5.2% increase in overall silicon area. Siyi Xu, Limin Jiang, Yintao Liu 0001, Yihao Shen, Yi Shi 0004, Shan Cao 0001, Zhiyuan Jiang |
LCTES | 1 |
| 2023 | Predicting Robustness Performance with Noises in Network RepresentationabstractThe connectivity and controllability of complex networks play an important role in ensuring the proper functioning of network systems. Robustness of connectivity and controllability is the ability of a network to maintain its basic functions against various malicious attacks. Convolutional neural network (CNN)-based approaches provide an efficient framework to approximate the network robustness, which significantly reduces computation time compared to attack simulations. In this paper, the performance of CNN-based prediction for connectivity and controllability robustness is investigated, when there are noises in the network input representation. Two CNN-based predictors are compared and investigated, 1) convolutional neural network-based robustness predictor (CNN-RP), and 2) spatial pyramid pooling-based convolutional neural network (CNN-SPP). Two aspects of network information noises are considered and investigated, 1) the random node information noises (RNIN), and 2) the random edge information noises (REIN). The following main conclusions are obtained from extensive experimental studies on synthetic networks: 1) CNN-RP is more tolerant than CNN-SPP to network noises, 2) The characteristics of small-world and scale-free networks make them have a favorable anti-noise ability, and 3) RNIN has less impact on CNN-based prediction performance than REIN, RNIN and REIN show opposite effects on prediction performance when the size of the predicted network is out of the training network size range. Chengpei Wu, Siyi Xu |
SMC | 2 |
| 2023 | A Nested Edge Addition Strategy for Network Controllability Robustness EnhancementabstractEdge rectification is a widely used method to enhance network robustness. However, in some networked systems, edge rectification may be challenging or even infeasible to implement. An edge addition strategy is proposed as an alternative optimization method in this paper. Nested Ring Structure (NRS), whereby each node's edges connect its nearest neighbors along the backbone direction, have exhibited robust controllability against random attacks. Therefore, The Nested Edge Addition (NEA) strategy is proposed, which enhances network controllability by building NRS through edge addition to a given initial network. With a small number of added edges, NEA can rapidly enhance network controllability, allowing the network to be controlled using just one driver node. The more nested edges are added, the stronger the NRS in a network, thus exhibiting better controllability robustness. The effectiveness of NEA is verified by simulations on both synthetic and real-world networks. Extensive experimental results demonstrate that NEA is an efficient strategy for designing network topology and optimizing real-world networks. Chengpei Wu, Siyi Xu, Zhuoran Yu |
SMC | 2 |
| 2021 | Collision Resilient Insect-Scale Soft-Actuated Aerial Robots With High AgilityabstractFlying insects are remarkably agile and robust. As they fly through cluttered natural environments, they can demonstrate aggressive acrobatic maneuvers such as backflip, rapid escape, and in-flight collision recovery. Current state-of-the-art subgram microaerial-vehicles (MAVs) are predominately powered by rigid actuators such as piezoelectric ceramics, but they have low fracture strength (120 MPa) and failure strain (0.3%). Although these existing systems can achieve a high lift-to-weight ratio, they have not demonstrated insect-like maneuvers such as somersault or rapid collision recovery. In this article, we present a 665 mg aerial robot that is powered by novel dielectric elastomer actuators (DEA). The new DEA achieves high power density (1.2 kW/kg) and relatively high transduction efficiency (37%). We further incorporate this soft actuator into an aerial robot to demonstrate novel flight capabilities. This insect-scale aerial robot has a large lift-to-weight ratio (>2.2:1) and it achieves an ascending speed of 70 cm/s. In addition to demonstrating controlled hovering flight, it can recover from an in-flight collision and perform a somersault within 0.16 s. This work demonstrates that soft aerial robots can achieve insect-like flight capabilities absent in rigid-powered MAVs, thus showing the potential of a new class of hybrid soft-rigid robots. Yufeng Chen 0003, Siyi Xu, Zhijian Ren, Pakpong Chirarattananon |
IEEE Trans. Robotics | 2 |