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Catherine Easdon

dblp:303/6604 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2022
0009-0001-7070-5589ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 94% Cryptographic primitives and cryptanalysis · 6%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
microarchitectural attacks
0.612022
Rapid Prototyping for Microarchitectural Attacks · USENIX Security Symposium 2022
Processor architecture and microarchitecture
microarchitectural security
0.612022
Rapid Prototyping for Microarchitectural Attacks · USENIX Security Symposium 2022
Hardware security and side channels › side-channel attack
power analysis
0.512021
PLATYPUS: Software-based Power Side-Channel Attacks on x86 · SP 2021
Hardware security and side channels › trusted execution environments
SGX attacks
0.512021
PLATYPUS: Software-based Power Side-Channel Attacks on x86 · SP 2021
Hardware security and side channels
side-channel attack
0.512021
PLATYPUS: Software-based Power Side-Channel Attacks on x86 · SP 2021
Hardware security and side channels
trusted execution environments
0.512021
PLATYPUS: Software-based Power Side-Channel Attacks on x86 · SP 2021
Cryptographic primitives and cryptanalysis › key generation
key extraction
0.112021
PLATYPUS: Software-based Power Side-Channel Attacks on x86 · SP 2021

Methods — techniques the papers use, named apart from their topics

rapid prototyping · 1.1statistical analysis · 0.5covert channel · 0.5RAPL interface · 0.5
YearPublicationVenuePosition
2022 Rapid Prototyping for Microarchitectural Attacks
Catherine Easdon, Michael Schwarz 0001, Martin Schwarzl, Daniel Gruss
USENIX Security Symposium1
2021 PLATYPUS: Software-based Power Side-Channel Attacks on x86
abstract
Power side-channel attacks exploit variations in power consumption to extract secrets from a device, e.g., cryptographic keys. Prior attacks typically required physical access to the target device and specialized equipment such as probes and a high-resolution oscilloscope.In this paper, we present PLATYPUS attacks, which are novel software-based power side-channel attacks on Intel server, desktop, and laptop CPUs. We exploit unprivileged access to the Intel Running Average Power Limit (RAPL) interface that exposes values directly correlated with power consumption, forming a low-resolution side channel.We show that with sufficient statistical evaluation, we can observe variations in power consumption, which distinguish different instructions and different Hamming weights of operands and memory loads. This enables us to not only monitor the control flow of applications but also to infer data and extract cryptographic keys. We demonstrate how an unprivileged attacker can leak AES-NI keys from Intel SGX and the Linux kernel, break kernel address-space layout randomization (KASLR), infer secret instruction streams, and establish a timing-independent covert channel. We also present a privileged attack on mbed TLS, utilizing precise execution control to recover RSA keys from an SGX enclave. We discuss countermeasures and show that mitigating these attacks in a privileged context is not trivial.
Moritz Lipp, Andreas Kogler, David F. Oswald, Michael Schwarz 0001, Catherine Easdon, Claudio Canella, Daniel Gruss
SP5