As computer architectures become increasingly complex and heterogeneous, it becomes progressively more difficult to write applications that make good use of hardware resources. Performance analysis tools are hence critically important as they are the only way through which developers can gain insight into the reasons why their application performs as it does. State-of-the-art performance analysis tools capture a plethora of performance events and are practically non-intrusive, but performance optimization is still extremely challenging. We believe that the fundamental reason is that current state-of-the-art tools in general cannot explain why executing the application's performance-critical instructions take time.

A fundamental part of developing software is to understand what the application spends time on. This is typically determined using a performance profiler which essentially captures how execution time is distributed across the instructions of a program. At the same time, the highly parallel execution model of modern high-performance processors means that it is difficult to reliably attribute time to instructions — resulting in performance analysis being unnecessarily challenging.

As programmable logic is conquering data centers, FPGA resources become a ubiquitously available commodity available through the cloud. In these ecosystems, their employment must advance to fit the role of a dynamically managed, shared resource within multi-user environments. Programmable hardware vendors provide engineering workflows that only start to acknowledge the requirements of this thriving application context, which makes resource regularization, design migratability and isolated execution imperatives. Quite a few academic efforts have aimed at the key technique of design relocation on top of the vendor-provided workflows. Regularly, critical shortcomings remain and, in all cases, the engineering procedure is ridiculously complex. This paper identifies the significant gaps left by previous approaches and describes a thoroughly automated workflow for building a system infrastructure on FPGA that makes it a resource that is manageable by the OS. It highlights an end-to-end workflow to enable (a) the out-of-context synthesis of end-user designs against a thin module interface defined by appropriate synthesis constraints, which are (b) universally employable to all the user slots provisioned on an appropriately partitioned device without re-synthesis and (c) will operate there appropriately isolated merely communicating to the user host application through privately allocated communication channels.