Demo Data from VLDB 2026 / reviewers in the wild / expert
HanCheon Yun
dblp:305/9484
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 40% Memory systems · 40% Integrated circuit design · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › processing-in-memory › computing-in-memory
analog in-memory computing |
0.5 | 1 | 2021 | Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator · DAC 2021 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.5 | 1 | 2021 | Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator · DAC 2021 |
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design |
0.5 | 1 | 2021 | Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator · DAC 2021 |
Memory systems
processing-in-memory |
0.5 | 1 | 2021 | Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator · DAC 2021 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN accelerator
ReRAM-based DNN accelerator |
0.5 | 1 | 2021 | Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator · DAC 2021 |
Methods — techniques the papers use, named apart from their topics
value-aware bypass · 0.5bit-line level value distribution · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN AcceleratorabstractReRAM-based Processing-In-Memory (PIM) has been widely studied as a promising approach for Deep Neural Networks (DNN) accelerator with its energy-efficient analog operations. However, the domain conversion process for the analog operation requires frequent accesses to power-hungry Analog-to-Digital Converter (ADC), hindering the overall energy efficiency. Although previous research has been suggested to address this problem, the ADC cost has not been sufficiently reduced because of its unsuitable approach for ReRAM. In this paper, we propose mixed-signal-based value-aware bypass techniques to optimize the ADC utilization of the ReRAM-based PIM. By utilizing the property of bit-line (BL) level value distribution, the proposed work bypasses the redundant ADC operations depending on the magnitude of value. Evaluation results show that our techniques successfully reduce ADC access and improve overall energy efficiency by 2.48 × -3.07 × compared to ISAAC. HanCheon Yun, Hyein Shin, Myeonggu Kang, Lee-Sup Kim |
DAC | 1 |