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Lianju Qian

dblp:306/0329 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 70% Cloud and datacenter computing · 23% Performance modeling and evaluation · 7%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
flash and SSD
0.512021
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs · ACM Trans. Archit. Code Optim. 2021
Storage systems › storage performance
i/o latency
0.512021
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs · ACM Trans. Archit. Code Optim. 2021
Storage systems
storage reliability
0.512021
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs · ACM Trans. Archit. Code Optim. 2021
Cloud and datacenter computing › quality of service
tail latency
0.512021
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs · ACM Trans. Archit. Code Optim. 2021
Performance modeling and evaluation
workload characterization
0.112021
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs · ACM Trans. Archit. Code Optim. 2021

Methods — techniques the papers use, named apart from their topics

mathematical modeling · 0.5fourier transform · 0.5
YearPublicationVenuePosition
2021 Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs
abstract
This article proposes a low I/O intensity-aware scheduling scheme on garbage collection (GC) in SSDs for minimizing the I/O long-tail latency to ensure I/O responsiveness. The basic idea is to assemble partial GC operations by referring to several determinable factors (e.g., I/O characteristics) and dispatch them to be processed together in idle time slots of I/O processing. To this end, it first makes use of Fourier transform to explore the time slots having relative sparse I/O requests for conducting time-consuming GC operations, as the number of affected I/O requests can be limited. After that, it constructs a mathematical model to further figure out the types and quantities of partial GC operations, which are supposed to be dealt with in the explored idle time slots, by taking the factors of I/O intensity, read/write ratio, and the SSD use state into consideration. Through a series of simulation experiments based on several realistic disk traces, we illustrate that the proposed GC scheduling mechanism can noticeably reduce the long-tail latency by between 5.5% and 232.3% at the 99.99th percentile, in contrast to state-of-the-art methods.
Zhibing Sha, Jun Li 0062, Lihao Song, Jiewen Tang, Min Huang 0018, Zhigang Cai, Lianju Qian, Jianwei Liao 0001, Zhiming Liu 0001
ACM Trans. Archit. Code Optim.7