Although offering great potential for energy-efficient edge-AI, memristor-based CIM accelerators are severely hindered by IR drop induced errors. To tackle this, we propose a low-cost mitigation technique by first quantifying the impact of IR drop on the accuracy. Then, a mitigation strategy is developed to compensate for IR drop-induced inference accuracy reduction by combining an optimized mapping scheme with a fine-tuned calibration of the ADC. Results show the proposed solution can effectively mitigate IR drop with a negligible overhead.

The objective of our collaborative multi-partner project is to create an open-source Deep Learning framework called AIDGE for edge and embedded Artificial Intelligence (AI), built around an established European value chain. The framework is designed to support diverse application domains that function independently while serving a broad international community. It offers an integrated, full-stack workflow from Neural Network design and optimization to AI application development and hardware-level implementation with automated code generation for specific hardware targets. The platform aims to provide researchers and developers with a flexible environment to explore novel AI concepts, rapidly prototype solutions, and ensure strong alignment between academic research and industrial requirements. This paper summarizes the progress, outcomes, and milestones achieved up to the second year of this three-year project.

The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

Computing-in-Memory (CIM) architectures using memristive crossbar arrays enable energy-efficient AI acceleration. Analog non-idealities, such as IR drop and nonlinearity, impose design constraints that existing simulators cannot capture and thus explore effectively. Current approaches sacrifice either modeling accuracy or simulation speed, preventing systematic design space exploration. In this paper we propose X-Sim, a crossbar simulator that resolves this trade-off through a modular architecture. Our approach decouples device physics from circuit analysis using a fixed-point scheme, avoiding expensive Jacobian computations while preserving device fidelity. X-Sim delivers SPICE-level accuracy (< 1% error) with up to 200× speedup over physics-based simulators. This enables quick and systematic design space exploration across thousands of configurations, guiding reliable system design. X-Sim will be released as open source.

Recent advances in Resistive RAM (RRAM) based Computation-In-Memory (CIM) architectures highlight significant potential for accelerating data-intensive computing tasks. However, non-idealities in RRAM devices, such as variability, result in small sensing margins that can significantly affect the computational efficiency. This issue becomes even more pronounced when dealing with complex multi-operand logic operations. This paper introduces a circuit-level scheme for CIM-based multi-operand XOR logic operations, leveraging a Voltage-To-Time converter (VTC) to perform multi-phased XORs in a single clock cycle. In this approach, we exploit bitline capacitances for voltage-based sensing during computation, generating an output voltage that is linearly proportional to the operand values. This voltage is then converted into the desired logic output using the VTC design. Furthermore, low-power techniques are employed in the deployment of sense amplifiers, such as regulating power consumption during operation and disabling the amplifiers once the decision is made. Simulation results for a post-layout extracted 512x512 (256Kb) RRAM-based CIM array show that up to 16-operand XOR operation can be accurately and reliably performed as opposed to a maximum of three operands supported by state-of-the-art solutions, while offering up to 49× better figure-of-merit combining energy-efficiency and throughput.