Processing-in-memory (PIM) architectures alleviate memory bottlenecks and improve latency and energy efficiency for AI and ML workloads by accelerating general matrix-vector multiplication (GEMV) operations in DNNs. However, permanent faults in arithmetic units (AUs) within processing units (PUs) critically impact yield and inference accuracy. Although the hybrid built-in self-test (HBIST) method has been proposed, it has limited capabilities in diagnosing and repairing faulty AUs within PUs. In this study, a novel Self-Test And Repair structure for PIM (STAR-PIM) is proposed to enable both fault diagnosis and repair by incorporating a bypass mechanism. A scan-path-like approach enables the testing and precise localization of faulty AUs, while faulty adders are bypassed using a redundant adder structure integrated within the memory die. Furthermore, faulty multipliers are masked using the weight-swapping logic. Experimental results demonstrate that STAR-PIM achieves high AU-level test coverage, ranging from 98.89% to 100% with reasonable area overhead. Recovery experiments show that STAR-PIM maintains low relative errors under fault rates up to 1% for GPT-2 and preserves inference accuracy under fault rates up to 3% for MNIST-MLP. Power measurements on GDDR6-AiM indicate an average overhead of 7.39% with only a 0.08% latency increase. Consequently, STAR-PIM significantly enhances the yield and reliability of PIM while reducing test costs, making it a highly practical solution.

The massive computational requirements of large language model (LLMs) have increased the need for high-bandwidth memory (HBM), which involves high-volume data transfers. The high cell capacity of HBM results in extended test and repair times, leading to increased manufacturing costs. To reduce test time, a built- in self-repair (BISR) circuit, integrated into the HBM base die to detect and repair faults, tests multiple banks in parallel. Conventional BISR approaches adopt content-addressable memory (CAM) for fault classification to reduce repair time. However, dedicated CAM on each bank leads to substantial area overhead associated with its comparison logic. To address these issues, a novel BISR architecture that decouples fault classification and storage is proposed in this article. By introducing a linked CAM design with low area and sharing it across banks for fault classification, while small-area first-in first-out (FIFO) memories allocated to each bank store the classified fault information, the proposed architecture substantially reduces overall area overhead. Furthermore, the proposed architecture reorders the repair solution search sequence toward the most promising candidates by swapping fault entries during test idle periods, thereby significantly reducing repair time. Experimental results demonstrate that the proposed BISR architecture achieves low area overhead and fast repair time for high-density HBM.

The increasing density of dynamic random access memory (DRAM) renders permanent faults and soft errors more prevalent, which critically reduces yield and reliability. Although error correction code (ECC) can mitigate this issue, existing ECCs are not optimized for fault correction. As a result, fault tolerance remains insufficient, and the error correction capability in the presence of faults is degraded. Therefore, to improve DRAM robustness by efficiently addressing both permanent faults and soft errors, this brief proposes a fault-aware adaptive on-die ECC (FADE) in which two ECC engines independently operate in either fault mode (FM) or error mode (EM) according to the number of faulty symbols (FSs). In FM, a fault polynomial is reconstructed by reusing the fault addresses that the built-in self-repair (BISR) stores in content-addressable memory (CAM). To calculate the corresponding fault magnitudes, a modified decoding equation is employed. As a result, the number of correctable FSs in FM doubles compared to the conventional ECC. Moreover, with the proposed symbol-based fault isolation, both fault tolerance and error correction capability in the presence of faults are drastically enhanced. Additionally, the experimental results show that the proposed design can be implemented with a reasonable overhead in terms of delay and area.

Scan-based testing is a widely used design for testability method to ensure the ease of testing. In this method, the enhanced observability and controllability provided by the inserted scan chains significantly improve the ability to analyze circuit data. However, since the enhanced testability can be exploited by malicious users as a backdoor for attacks, countermeasures need to be implemented to prevent scan chain access by unauthorized users. Although much research on secure scan designs has been conducted, most proposed methods are vulnerable to architecture exposure by reverse engineering. Moreover, even the latest proposed methods are affected by issues related to untrustworthy test engineers. This study proposes a pattern-sequence-authentication-based secure scan that not only defends against reverse engineering-based attacks but also prevents test engineers from launching attacks using additional patterns other than the given pattern. The proposed method effectively addresses the issue of secret key leakage through valid test patterns by untrustworthy test engineers, which is a limitation of the existing methods. The experimental results show that the proposed method effectively defends against existing attack techniques and ensures high security performance.

High bandwidth memory (HBM) represents a significant advancement in memory technology, requiring quick and accurate data processing. Built-in self-repair (BISR) is crucial for ensuring high-capacity and reliable memories, as it automatically detects and repairs faults within memory systems, preventing data loss and enhancing overall memory reliability. The proposed BISR aims to enhance the repair rate and reliability by using a content-addressable memory structure that operates effectively in both offline and online modes. Furthermore, a new redundancy analysis algorithm reduces both analysis time and area overhead by converting fault information into a matrix format and focusing on fault-free areas for each repair solution. Experimental results demonstrate that the proposed BISR improves repair rates and derives a final repair solution immediately after the test sequences are completed. Moreover, hardware comparisons have shown that the proposed approach reduces the area overhead as memory size increases. Consequently, the proposed BISR enhances the overall performance of BISR and the reliability of HBM.

Errors emerge as a major issue in the reliability of dynamic random access memory (DRAM). To enhance reliability, a two-tiered error correction code (ECC) architecture that comprises on-die ECC (OD-ECC) and system ECC (S-ECC) is adopted as a part of the standard for state-of-the-art high-bandwidth memory (HBM). However, conventional ECCs are insufficient to mitigate malfunctions of subwordline drivers (SWDs), a primary cause of errors. Moreover, the efficient co-design of two-tiered ECCs has not been sufficiently studied. To address these issues without increasing the size of check bits, this article proposes a two-tiered ECC architecture comprising an OD-ECC based on prediction and an S-ECC with data deinterleaving. The proposed OD-ECC predicts the SWD errors by leveraging the detection capabilities of two interleaved Reed-Solomon (RS) engines. In addition, the proposed S-ECC not only preserves strong error detection capability but also masks the misprediction effect of OD-ECC, where data deinterleaving renders additional errors caused by misprediction of OD-ECC to be bounded in the detectable range of the employed cyclic redundancy check (CRC). The experimental results demonstrate that the proposed two-tiered ECC can significantly enhance the error correction capability for SWD errors while maintaining the correction capability for other types of errors.