The goal of design and technology co-optimization (DTCO) is to find a combination of parameter options (i.e., parameter setting values) of target process technology that enables to produce a target design implementation of optimal PPA (performance, power, area). Since the number of parameters sharply increases as the technology scales, recently, lots of attention has been paid to automating this DTCO process in both semiconductor foundry and academic research community. This paper addresses the problem of a full DTCO automation that deals with analyzing the numerous parameter options at advanced technology nodes. Precisely, we develop a machine learning (ML) based DTCO automation framework, which supports three key features: (1) an effective analysis on the changes of DTCO parameter options within an acceptable runtime; (2) a full exploration of chip/block-level PPA metrics through automatic standard cell (SC) library generation, for which we develop a new technique that enables to accelerate the iterative physical design process; (3) supporting both of Complementary FET (CFET) based SCs and multi-row-height SCs to account for future generation technology. Through experiments with benchmark circuits, it is shown that our DTCO automation framework is able to accurately predict the direction and magnitude of PPA changes of target designs with 5x sampling efficiency. In addition, it is shown that our SC layout generator supporting CFET and multi-rowheight SCs provides a timely DTCO process relevant to ongoing technology advancements.

This paper presents a new approach to the problem of improving pin accessibility, which has become an important task for physical design at the advanced technology nodes. To this end, we propose a new concept, called disclosed-pins, which allows to daringly expose some pins of standard cells across the cell boundary, which otherwise, there would be no way to boost pin accessibility. However, it requires two key issues that should be resolved to make the disclosed-pin concept fully effective. Those are (1) how can we systematically synthesize diverse structures of standard cells with disclosed-pins? and (2) how can we effectively exploit those cells in the course of chip implementation? Precisely, for issue 1, we propose a new in-cell routing method combined with disclosed-pin generation, developing it based on an SMT (satisfiability modular theory) formulation, while for issue 2, we develop a post-place optimization, in which we optimally replace, on a row-basis, the cell instances with low pin accessibility in a row by the cells with disclosed-pins, formulating it into an instance of DP (dynamic programming). In the meantime, through experiments with benchmark circuits, it is shown that our proposed methodology utilizing our synthesized cells with disclosed-pins can considerably relieve the burden in block-level routing, resulting in reducing the number of design rule violations by 26.05% and 22.80% on average over that produced by the state-of-the-art prior methods of pin pattern (internal) extension and dummy poly insertion, respectively.

As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, for the sequential cells on the timing critical paths in circuits, there is no easy way for the multi-VT method to reduce the leakage power unless timing is not sacrificed. To overcome this barrier, we introduce a set of new standard cells called hybrid-VT flipflop cells, each of which is implemented with two different VT types, one implanted onto its master latch while the other onto its slave latch, by which the setup time and clock-to-Q delay can be controlled individually and independently. We confirm that applying our power recovery method utilizing hybrid-VT flipflop cells to the benchmark circuits, which have already been optimized by the conventional multi-VT cells, is able to further reduce the leakage power by 8.97% with no timing degradation.

In deep-submicron technology nodes, I/O pin accessibility on the cells is crucial for successful net routing in physical design. For this reason, the conventional design flows have paid a considerable attention to acquiring the cell library with high pin accessibility to facilitate the net routing task. Nevertheless, the increase in routing failures is inherently unavoidable as the cell size shrinks with the progress of the technology node. In this context, this work proposes a new technique called adaptive pin-pattern modification (APM) to tackle this fundamental problem. Precisely, our proposed ECO-routing method based on adaptive pin-pattern modification makes use of three novel pin-pattern modifications on standard cells, which are referred to as pin-shift-trim (PST), pin-free (PF) and pin-bridge (PB). By applying these pin-pattern modifications adaptively and systematically to suit the circumstances to the individual cell instances with pin access failure, our ECO-router is able to explore the routable paths more extensively and effectively over the sequential, maze-routing based, ECO-routers but spend a much shorter time over the concurrent ECO-routers. Experimental results show that our proposed APM-enabled ECO-router resolves 17.7% of pin inaccessibility cases that a commercial tool has failed to find legal routes, with no penalty of chip PPA, and achieves over 116x speedup compared to the concurrent MCF (multi-commodity flow) based ECO-router.

In this paper, a new approach to the problem of synthesizing standard cells is presented. The top priority objective in the conventional approaches has been invariably placed on minimizing cell area. However, in our approach, we place the top priority on minimizing cell delay as opposed to minimizing cell area, which has never been addressed as yet, but is very valuable and highly important for implementing high-performance chips at advanced technology nodes. Precisely, we propose a totally different approach, developing a cell delay driven layout synthesis method, which is composed of three steps: (1) a critical path driven transistor placement, which is formulated into a search tree based exhaustive placement enumeration, employing an effective pruning technique, followed by (2) an optimal transistor folding, formulating it into an instance of DP (dynamic programming) to reduce cell area by maximizing the occurrences of diffusion sharing and minimizing the oxide diffusion jog rule violations, then (3) an optimal critical net driven in-cell routing, formulating it into an instance of SMT (satisfiability modulo theory) problem. In the meantime, through experiments with benchmarks, it is shown that our cell synthesis approach is able to produce cells with up to 9.3% shorter delay. More importantly, by using those cells, we are able to increase the circuit clock frequency by 7.2% on average while retaining nearly the same chip area and power consumption over that produced by using the conventional cells.

To generate standard cell (SC) layouts of competitive quality, pin accessibility and in-cell routing congestion should be thoroughly taken into account. In this work, we develop a new tool to address this issue. Precisely, we (1) develop a technology compilation module that can convert diverse cell architectures and design rules into grid based design parameters and layer configuration, (2) generate optimal FET placement using metrics that can accurately and efficiently predict intra-cell pin accessibility and in-cell routing congestion, and (3) introduce the concept of ghost-via and ghost-metal, and formulate in-cell routing using satisfiability modulo theory for pin separation and extension. Experimental results show that our system is able to synthesize SC layouts with a routing completion rate of 95~98 %, which is far better than the previous SC layout generator, and produce layouts comparable to the ARM's hand-crafted layouts. In addition, the design implementations produced by using our 2-layer ID SC library exhibit on average 76.6% fewer design rule violations (DRVs) with similar or better quality of timing and area, while in comparison with that produced by using the library of hand-crafted ARM SCs, the implementations produced by using our L-layer 2D SC library exhibit on average 11.7% smaller area with comparable timing and DRV count.

In this paper, we address three core problems in the layout synthesis of multi-row standard cells: transistor folding, row partitioning, and transistor placement. We propose a comprehensive solution to the problem of synthesizing area-optimal multi-row standard cells by seamlessly integrating transistor folding and row partitioning into the transistor placement framework. Additionally, we introduce a systematic methodology to construct a standard cell library. This methodology determines the cell types among single-row, multi-row with VDD-abut, and multi-row with VSS-abut in order to achieve an optimal trade-off between power, performance, and area (PPA) for the target design implementation. Experimental results demonstrate that for 4-routing track standard cells of the advanced technology nodes our multi-row cell generator increases the cell generation completion ratio from 72% to 100% and reduces the metal length for in-cell routing by 11.9% while maintaining comparable cell area compared to the area-minimal single-row cells. Furthermore, using our optimized cell library is able to reduce the target chip area by 4.2% and chip power by 7.0%, while all meeting timing and design rule constraints, compared to the state-of-the-art single-row standard cell library.

Traditionally, the synthesis of standard cells invariably assumes that the gear ratio (GR) between the gate poly pitch in the cells and the metal pitch of the first vertical metal layer (to be used for routing) over the gate poly is 1:1 for chip implementation. However, the scaling trend in sub-10nm node CMOS designs is that GR is changing from 1:1 to 3:2 or 4:3, which means the number and location of pin access points vary depending on the cell placement location, thereby causing hard-to-pin-access if the pin access points were aligned on the off-track routing pattern. This work overcomes the pin inaccessibility problem caused by non-1:1 GR in chip implementation. Precisely, we propose a non-1:1 GR aware DTCO (design and technology co-optimization) flow to generate cells with pin patterns that are best suited to the implementation of target design. To this end, we propose two new tasks to be installed in our DTCO framework: (1) from the existing cells optimized for 1:1 GR, we relocate their pin patterns amenable to non-1:1 GR, so that a maximal pin accessibility should be achieved; (2) we incrementally update the pin patterns of the cell instances with routing failures due to pin inaccessibility in the course of the DTCO iterations to produce the cells with best fitted pin patterns to the implementation of target design. We formulate task 1 into a problem instance of dynamic programming to find an optimal solution of pin positions, considering design rule and access conflict constraints while we solve task 2 by devising an assessment function on the pin accessibility enhanced by pin pattern extension to find out the most suitable direction for the extension. In the meantime, through experiments with benchmark circuits, it is shown that our DTCO methodology optimizing pin patterns amenable to non-1:1 GR is able to produce chip implementations with on average 5.88 × fewer routing failures at no additional wirelength, timing, and power cost.

This paper addresses the combined problem of the three core tasks, namely routing on the middle-of-line (MOL) layer, generating I/O pin patterns (PP), and allocating contacts over active gates (COAG) in cell layout synthesis with 7nm and below technology. As yet, the existing cell layout generators have paid partial or little attention to those tasks, even with no awareness of the synergistic effects. This work overcomes this limitation by proposing a systematic and tightly-linked solution to the combined problem to boost the synergistic effects on chip implementation. Precisely, we solve the problem in three steps: (1) fully utilizing the horizontal routing resource on MOL layer by formulating the problem of in-cell routing into a weighted interval scheduling problem, (2) simultaneously performing the remaining horizontal in-cell routing and PP generation on metal 1 layer through the COAG exploitation while ensuring the pin accessibility constraint, and (3) completing in-cell routing by allocating vertical routing resource on MOL layer. Through experiments with benchmark designs, it is shown that our proposed layout method is able to generate standard cells with on average 34.2% shorter total length of metal 1 wire while retaining pin patterns that ensure pin accessibility, resulting in the chip implementations with up to 72.5% timing slack improvement and up to 15.6% power reduction that produced by using the conventional best available cells. In addition, by using less wire and vias, our in-cell router is able to consistently reduce the worst delay of cells, noticeably, reducing the sum of setup time and clock-to-Q delay of flip-flops by 1.2% ∼ 3.0% on average over that by the existing best cells.

Monolithic 3D (M3D) is a revolutionary technology for high-density and high-performance chip design in the post-Moore era. However, it suffers from considerable thermal confinement due to the transistor stacking and insulating materials between the layers. As a way of reducing power, thereby mitigating the thermal problem, we propose a comprehensive physical design methodology that incorporates two new important items, one is blockage aware MIV (monolithic inter-tier via) placement and the other is 3D net ordering for routing, intending to optimize wire length. Precisely, we propose a three-step approach: (1) retrieving the MIV region candidates for each 3D net, (2) fine-tuning placement to secure MIV spots in the presence of blockages, and (3) performing M3D routing with net ordering to consider the fine-tuned placement result. We implement the proposed M3D design flow by utilizing commercial 2D IC EDA tools while providing seamless optimization for cross-tier connections. In the meantime, our experiments confirm that proposed M3D design flow saves wire length per cross-tier net by up to 41.42%, which corresponds to 7.68% less total net switching power, equivalently 36.79% lower energy-delay-product over the conventional state-of-the-art M3D design flow.