Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Xiangren Chen

dblp:308/9050 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Memory systems · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.612022
Efficient access scheme for multi-bank based NTT architecture through conflict graph · DAC 2022
Memory systems › memory architecture
multi-bank memory
0.612022
Efficient access scheme for multi-bank based NTT architecture through conflict graph · DAC 2022
Hardware accelerators and domain-specific architectures › cryptographic accelerator
number theoretic transform architecture
0.612022
Efficient access scheme for multi-bank based NTT architecture through conflict graph · DAC 2022

Methods — techniques the papers use, named apart from their topics

conflict graph heuristic · 0.6
YearPublicationVenuePosition
2022 Efficient access scheme for multi-bank based NTT architecture through conflict graph
abstract
Number Theoretical Transform (NTT) hardware accelerator becomes crucial building block in many cryptosystems like post-quantum cryptography. In this paper, we provide new insights into the construction of conflict-free memory mapping scheme (CFMMS) for multi-bank NTT architecture. Firstly, we offer parallel loop structure of arbitrary-radix NTT and propose two point-fetching modes. Afterwards, we transform the conflict-free mapping problem into conflict graph and develop novel heuristic to explore the design space of CFMMS, which turns out more efficient access scheme than classic works. To further verify the methodology, we design high-performance NTT/INTT kernels for Dilithium, whose area-time efficiency significantly outperforms state-of-the-art works on the similar FPGA platform.
Xiangren Chen, Bohan Yang 0001, Shouyi Yin, Shaojun Wei, Leibo Liu
DAC1