Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Sushma Yellapragada

dblp:309/5377 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 67% Electronic design automation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing › GPU computing › GPGPU acceleration
GPU-accelerated EDA
0.712023
A GPU-Accelerated Framework for Path-Based Timing Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
GPUs and heterogeneous computing
GPU computing
0.712023
A GPU-Accelerated Framework for Path-Based Timing Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Electronic design automation › timing analysis
static timing analysis
0.712023
A GPU-Accelerated Framework for Path-Based Timing Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

GPU kernel optimization · 0.7
YearPublicationVenuePosition
2023 A GPU-Accelerated Framework for Path-Based Timing Analysis
abstract
As a key routine in static timing analysis (STA), path-based analysis (PBA) plays a very important role in refining the critical path report by reducing excessive slack pessimism. PBA is also well known for its long execution time, which makes it a hot topic for parallel computing in the STA community. However, nearly all of the parallel PBA algorithms are restricted to CPU architectures, which greatly limits their scalability. To achieve a new performance milestone on PBA, we must leverage the high throughput computing in the graphics processing unit (GPU). Therefore, in this work, we propose a new GPU-accelerated PBA framework which contains compact data structures and highly efficient kernels. By integrating with GPU-accelerated preprocessing steps, our framework can also effectively handle extensive critical path constraints. Besides, we highlight many optimization techniques that can overcome the execution bottleneck and further boost the performance. In experiments, we demonstrate$543\times$speed-up compared to the state-of-the-art PBA algorithm on the design with 1.6 million gates, which outperforms$25\times $–$45\times$over the state-of-the-art parallel PBA algorithm on 40 CPU cores. A fully optimized framework can achieve$3\times$–$5\times$speed-up on top of that.
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo 0001, Sushma Yellapragada, Martin D. F. Wong
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5