VLDB 2026 Research / reviewers in the wild / expert
Xijin Yin
dblp:309/5630
· DBLP profile ↗
5ranked-venue papers
2as first author
5since 2021 · last 2026
0009-0003-6942-7897ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 5 · 2 first-author · 5 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | BURST: Seeking High-performance, Interoperability and Scalability in Soft-RDMA
Huijun Shen, Zelong Yue, Zhuo Jiang, Lang An, Luochangqi Ding, Xiaolong Zhong, Jianxi Ye, Xijin Yin, Xingyu Guo |
NSDI | 14 |
| 2026 | Advancing RDMA Scalability With High PerformanceabstractDue to its superior performance, Remote Direct Memory Access (RDMA) has been widely deployed in data center networks. It provides applications with ultra-high throughput, ultra-low latency, and far lower CPU utilization than TCP/IP software network stack. However, the connection states that must be stored on the RDMA NIC (RNIC) and the small NIC memory result in poor scalability. The performance drops significantly when the RNIC needs to maintain a large number of concurrent connections. We propose StaR (Stateless RDMA), which solves the scalability problem of RDMA by transferring states to the other communication end in a trusted network. Leveraging the asymmetric communication pattern in data center applications, StaRlets the communication end with low NIC memory usage to save states for the other end with high NIC memory usage, thus making the RNIC on the bottleneck side stateless. We implemented StaR on an FPGA board with a 10Gbps network port and NS-3, evaluating its performance on a testbed with 9 machines, each equipped with StaR NICs, and verified its scalability stability by conducting a larger-scale simulation with 200 fully connected nodes using a 100Gbps link. The experimental results show that in high concurrency scenarios, the throughput of StaR can reach up to 4.13x and 1.35x of the original RNIC and the latest software-based solution, respectively. Xijin Yin, Guo Chen 0001, Xizheng Wang, Huichen Dai, Bojie Li, Binzhang Fu, Kun Tan 0002 |
IEEE Trans. Netw. | 1 |
| 2026 | Accelerating Hardware/Software Combined Traffic Processing With Fast and Efficient Asynchronous Flow OffloadingabstracteHardware/software (hw/sw) combined systems are necessary to meet modern clouds’ requirements for processing huge amounts of network traffic by efficiently offloading large flows to hardware. However, existing hw/sw flow offloading systems typically perform traffic statistics collection and large flow selection within a time window—a time-window-based approach. Their offloading decision of large flows issynchronizedin the unit of a time window, which is mismatched to the asynchronous and dynamic nature of each flow’s sending rate. Additionally, the flow measurement and selection for large flows are decoupled in these solutions, leading to memory and CPU inefficiency. In this paper, we introduce TAO, a novel solution to the hw/sw combined flow offloading problem byasynchronouslyselecting and offloading flows based on flow table entries. TAO can reactfasterto the rapid dynamics of flows by taking actions at each table entry and ismore efficientby coupling flow measurement and selection into the entry. We have implemented a full-fledged TAO prototype based on the P4 switch and DPDK. Testbed results demonstrate that TAO can offload ∼16% more traffic to hardware, outperforming existing solutions by achieving 42× lower memory overhead. Meanwhile, it reduces software CPU utilization by 66.7% and cuts tail forwarding latency by 95.59% compared to state-of-the-art methods. Xijin Yin, Yuanwei Lu, Xin Zhang 0117, Xingtong Lin, Shengli Zheng, Bangwen Deng, Xianneng Zou, Yachen Wang, Guo Chen 0001 |
IEEE Trans. Netw. | 1 |
| 2025 | UCM: Fast and Maintainable User-space RDMA Connection Setup
Huijun Shen, Zelong Yue, Xingyu Guo, Xijin Yin, Lang An, Jianxi Ye, Guo Chen 0001 |
APNet | 5 |
| 2021 | StaR: Breaking the Scalability Limit for RDMAabstractDue to its superior performance, Remote Direct Memory Access (RDMA) has been widely deployed in data center networks. It provides applications with ultra-high throughput, ultra-low latency, and far lower CPU utilization than TCP/IP software network stack. However, the connection states that must be stored on the RDMA NIC (RNIC) and the small NIC memory result in poor scalability. The performance drops significantly when the RNIC needs to maintain a large number of concurrent connections.We propose StaR (Stateless RDMA), which solves the scalability problem of RDMA by transferring states to the other communication end. Leveraging the asymmetric communication pattern in data center applications, StaR lets the communication end with low concurrency save states for the other end with high concurrency, thus making the RNIC on the bottleneck side to be stateless. We have implemented StaR on an FPGA board with 10Gbps network port and evaluated its performance on a testbed with 9 machines all equipped with StaR NICs. The experimental results show that in high concurrency scenarios, the throughput of StaR can reach up to 4.13x and 1.35x of the original RNIC and the latest software-based solution, respectively. Xizheng Wang, Guo Chen 0001, Xijin Yin, Huichen Dai, Bojie Li, Binzhang Fu, Kun Tan 0002 |
ICNP | 3 |