Burhanuddin Bharmal

dblp:309/6855 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 50% Hardware reliability and fault tolerance · 50%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Embedded and real-time systems › real-time scheduling
mixed-criticality scheduling
0.712023
RTailor: Parameterizing Soft Error Resilience for Mixed-Criticality Real-Time Systems · RTSS 2023
Embedded and real-time systems
real-time scheduling
0.712023
RTailor: Parameterizing Soft Error Resilience for Mixed-Criticality Real-Time Systems · RTSS 2023
Hardware reliability and fault tolerance
soft errors
0.712023
RTailor: Parameterizing Soft Error Resilience for Mixed-Criticality Real-Time Systems · RTSS 2023
Hardware reliability and fault tolerance › soft errors
soft error resilience
0.712023
RTailor: Parameterizing Soft Error Resilience for Mixed-Criticality Real-Time Systems · RTSS 2023
Compilers and program optimization
compiler-based fault tolerance
0.212023
RTailor: Parameterizing Soft Error Resilience for Mixed-Criticality Real-Time Systems · RTSS 2023

Methods — techniques the papers use, named apart from their topics

schedulability analysis · 1.3loop transformation · 1.3
YearPublicationVenuePosition
2023 RTailor: Parameterizing Soft Error Resilience for Mixed-Criticality Real-Time Systems
abstract
Equipping real-time systems with soft error resilience can be challenging due to the tradeoff of the timing and failure requirements for mixed-criticality tasks. Violation of these requirements yields failed task scheduling in one way or another. However, not every task requires the same degree of soft error resilience. For example, low-criticality tasks can run with low or even no soft error resilience, whereas mid- or highcriticality tasks may require relatively high resilience depending on their inherent failure requirement. Unfortunately, existing soft error resilience schemes do not have the ability to control the degree of their resilience in a fine-grained way, i.e., they can only be turned on or off as a whole during task execution. To this end, this paper presents RTailor (Resilience Tailor), a compiler-directed parameterized soft error resilience scheme that achieves the desired level of soft error protection according to the demand of each task. The key idea is that for a given protection ratio, compilers can transform a hot loop such that the number of its iterations protected over the total iterations matches the ratio. Compared to full resilience protecting every iteration, RTailor's parameterized soft error resilience significantly reduces the performance overhead of tasks, thereby improving their real-time schedulability. The experimental results highlight that for four representative fault rates, RTailor achieves 15%~average schedulability improvements over the state-of-the-art work that lacks parameterized soft error resilience.
Shao-Yu Huang, Jianping Zeng 0001, Xuanliang Deng, Sen Wang 0014, Ashrarul H. Sifat, Burhanuddin Bharmal, Jia-Bin Huang 0001, Ryan K. Williams, Haibo Zeng 0001, Changhee Jung
RTSS6