This work presents a novel low-power, mixed-signal computing in memory (CIM) architecture for Bayesian inspired inference, targeting edge AI applications requiring energy-efficient uncertainty estimation. Our system integrates a deterministic Binary Neural Network (BNN) with a Bayesian head module implemented using multi-pillar (MP) Spin-Orbit Torque Magnetic RAM (SOT-MRAM) based arrays. The Bayesian head perturbs the output popcount of the BNN by injecting configurable stochastic counts, enabling uncertainty quantification in classification tasks. These perturbations are configurable in ‘flavor’ through a tunable dropout rate and the number of MP cells. A VCO-based ADC converts analog resistive summations into digital counts, which are then combined with the deterministic BNN output. On MNIST and CIFAR-10, the proposed system achieves classification accuracy comparable to state-of-the-art Bayesian approaches while consuming only 19 µW. It achieves a favorable energy efficiency of 53 TOPs/W (18.9 fJ/OPS) for 3-bits and 110 TOPs/W for 2-bits perturbation precision. Uncertainty estimation is validated through controlled domain shifts (e.g., tilted images), showing robust entropy and variance evolution. Notably, the proposed uncertainty estimation requires only 25 perturbation runs, resulting in a total energy cost of just 454 fJ. At this overhead, the Bayesian-inspired model improves reliability by 34.29% compared to the baseline on CIFAR-10. This low-power hybrid analog-digital architecture offers a promising solution for edge applications with embedded confidence metrics.

We present an integrated circuit fabricated in a process co-integrating CMOS and hafnium-oxide memristor technology, which provides a prototyping platform for projects involving memristors. Our circuit includes the periphery circuitry for using memristors within digital circuits, as well as an analog mode with direct access to memristors. The platform allows optimizing the conditions for reading and writing memristors, as well as developing and testing innovative memristor-based neuromorphic concepts.

Bayesian reasoning is a machine learning approach that provides explainable outputs and excels in small-data situations with high uncertainty. However, it requires intensive memory access and computation and is, therefore, too energy-intensive for extreme edge contexts. Near-memory computation with memristors (or RRAM) can greatly improve the energy efficiency of its computations. Here, we report two fabricated integrated circuits in a hybrid CMOS-memristor process, featuring each sixteen tiny memristor arrays and the associated near-memory logic for Bayesian inference. One circuit performs Bayesian inference using stochastic computing, and the other uses logarithmic computation; these two paradigms fit the area constraints of near-memory computing well. On-chip measurements show the viability of both approaches with respect to memristor imperfections. The two Bayesian machines also operated well at low supply voltages. We also designed scaled-up versions of the machines. Both scaled-up designs can perform a gesture recognition task using orders of magnitude less energy than a microcontroller unit. We also see that if an accuracy lower than 86.9% is sufficient for this sample task, stochastic computing consumes less energy than logarithmic computing; for higher accuracies, logarithmic computation is more energy-efficient. These results highlight the potential of memristor-based near-memory Bayesian computing, providing both accuracy and energy efficiency.