The aim of this new hardware description language, Descriptive Techniques for Modules and Systems II (DTMSII), is to enhance mixed level descriptions and multilevel modeling of interconnected digital systems [1][2][3]. The focus in DTMSII is on the description of the functional behavior of digital modules coupled with a detailed description of module interactions. Processor and related modules can be described at a high level of abstraction wherein the hardware details internal to the module are suppressed. On the other hand, module interconnection structures and interactions among the modules are carefully detailed at a low level of abstraction. DTMSII has powerful constructs to specify nonprocedural actions, serial and parallel updates, and zero and nonzero time delays. An almost unlimited amount of parallelism is possible in DTMSII. Both synchronous and asynchronous operations can be specified. Important language features and constructs are illustrated in the description of an M6800 microprocessor system. Quite different examples studied by the authors are available in the references.

This correspondence describes a special purpose Asynchronous Circuit Design Language (ACDL) for specifying the terminal behavior of asynchronous sequential circuits. The language is a valuable tool for formalizing and documenting asynchronous designs, as well as providing a user interface to a completely automated synthesis system. The language includes many special features which permit quick and precise specification of terminal behavior and is best suited for problems that are currently being described informally by word statements.

FLOWWARE is an interactive, graphical language to aid in the understanding and design of digital networks. The language is based upon the concept of flow charting. The user specifies the register layout of the network and the sequential operation in the form of a flow chart on a graphics terminal. The flow chart allows a user who is unfamiliar with the network to easily understand the function and operation of the network.

This paper presents a new procedure for constructing nonuniversal shared-row internal state assignments for asynchronous sequential circuits. The method consists basically of establishing an initial code with the minimum number of variables required to distinguish the states. satisfactory assignment is obtained. State variables added in the expansion of an assignment are merely the EXCLUSIVE OR of state variables in the original assignment. This simple construction procedure terminates with a maximum of m+[m/2] state variables for a 2m-row flow table.

Described here is a linear code that has a maximum distance between codewords ofkfor a code of order2^k. Since the minimum-maximum distance iskfor a code of order2^k, a class of minimum-maximum distance codes results. For an(n,k)linear code,k \leq n \leq k + k/2forkeven andk \leq n \leq k + (k - 1)/2forkodd. Maximum-distance codes are found useful in encoding the states of sequential circuits.

Methods already exist for the construction of critical race-free assignments for asynchronous sequential circuits. Some of these methods permit the construction of many assignments for the same flow table. The algorithm presented here consists of two easy to apply tests which select that critical race-free assignment most likely to produce a set of simple next-state equations. The algorithm has been programmed.

One step in the synthesis procedure for realizing an asynchronous sequential switching circuit is the generation of next-state and output state equations from a simplified and coded flow table description of the circuit. The usual approach for determining these equations is to first construct a state table from the coded flow table, and then construct transition and output tables. For large flow tables this can be quite a lengthy procedure. This note describes an algorithm which simplifies the synthesis procedure for normal fundamental-mode circuits by permitting the determination of these equations without explicit construction of the state table, transition table, or output table. The algorithm has been programmed in PL/1.

The paper presents three procedures for coding the internal states of asynchronous sequential switching circuits. Resulting codes insure that the circuit will function according to flow table specifications independent of variations in transmission delays within the circuit. The assignment methods produce codes that allow one to maximize the operating speed of the circuit and are applicable to completely or incompletely specified sequential machines.