The rapid development of smart medical systems has significantly increased the importance of cybersecurity. If edge medical devices are compromised, patients’ private data could be stolen and used for improper purposes, and if the device identity is forged, it could lead to serious consequences. In this study, we proposed and applied a PUF-based secured smart healthcare system to the real-time respiratory disease diagnosis system. For this system, the PUF security chip is integrated and provides identity authentication, preventing the identity of edge devices from being forged. Additionally, all data transmission is encrypted, protecting patients’ private information. The PUF security technology ensures that no one can steal the security keys, making this a highly secure smart medical device.

This study proposes a Physical Unclonable Function (PUF)-based end-to-end mutual authentication security protocol that generates authentication parameters through elliptic curve encryption and biometric identification. The protocol effectively resists various attacks while offering a high-performance system that does not require real-time server involvement. Through testing and security analysis, the proposed protocol has proven to be practical for deployment in various scenarios.

In recent years, the complexity of neural network (NN) models has increase continuously, resulting in a substantial increase in multiply-accumulate (MAC) operations. Therefore, the need for area- and power-efficient DRAM compute-in-memory (CIM) designs has become a pressing issue. The proposed CIM design uses the reverse rotating charge sharing (RRCS) technique to save 79% of silicon area compared to conventional designs. In addition, the use of the proposed low-threshold prediction technique can reduce analog-to-digital converter (ADC) calculations by 25% and ADC power consumption by 17%. Energy efficiency and area reduction are 10x and 1900x, respectively, higher than previous CIM designs.

Elliptic Curve Cryptography (ECC) is a significant asymmetric encryption technique, with Elliptic Curve Multiplication (ECM) playing a fundamental role in ECC. However, the conventional ECM employs the Double-and-Add algorithm, which sequentially processes each private key bit, making it vulnerable to Side-Channel Attacks (SCAs). To address this issue, this paper proposes a method that transforms the private key into a variable-radix system for computation. By breaking the correlation between private key bits and power waveforms, this design effectively defends against various forms of SCAs, including Timing Attacks (TA), Simple Power Analysis (SPA), Differential Power Analysis (DPA), Doubling Attacks, and Zero Point Attacks (ZPA), and we implemented our design using TSMC 40nm process.

The rapid growth of AI and IoT has transformed healthcare through emotion recognition using physiological signals like EEG, promising applications in clinical psychology, human-computer interaction, and personalized healthcare. However, the challenge of real-time emotion recognition requires effective solutions for hardware cost and computational speed. This paper proposes an edge AI accelerator design based on the Hyperdimensional Computing (HDC) model, utilizing a FPGA and RISC-V platform for real-time emotion recognition system using EEG signals. The HDC model offers benefits in power efficiency and computational complexity compared to traditional neural networks, making it suitable for resource-constrained IoT devices and edge computing. The proposed hyperdimensional computing model achieved high accuracy in the analysis of emotion from 17-channel EEG data, with 79.04% accuracy for valence and 85.95% accuracy for arousal. Additionally, our hardware design achieved 500 MHz and 42.69 nJ/prediction in TSMC 16 nm technology simulation, which is 2.1 times energy efficiency improvement than traditional AI.

Photoplethysmography (PPG) is a convenient and anti-counterfeiting method for identity authentication. However, traditional PPG authentication methods encounter challenges when adding new users, as model adjustments can lead to unstable performance. To address this, we trained a feature embedding model using a loss function to capture feature differences and extract vectors for similarity evaluation. This approach allows our model to recognize new users without adjustments or retraining, ensuring stability and scalability. Additionally, we propose a Dynamic Weighted Triplet Loss (DW Triplet Loss) that considers both distance magnitude and similarity. This enhancement improves distance perception, leading to a more stable similarity evaluation and better threshold determination for class classification. Our model achieves an accuracy of 97.4% and an equal error rate of 2.3% with a low false rejection rate of 4.6% at 1% false acceptance rate, making it suitable for reliable PPG authentication systems.

In this paper, we proposed an area-efficient hardware implementation of modular inversion/division, which is a complex and crucial component in elliptic curve cryptography (ECC). Our modular inversion/division is based on our modified binary inversion algorithm. The proposed hardware implementation of modular inversion/division improves the area efficiency and was designed and implemented on Xilinx Spartan-6 and Virtex-7 field-programmable gate array (FPGA) platforms and simulated with TSMC 90nm and 180nm technology nodes. Our proposed modular inversion/division is suitable for prime fields used in public key cryptography, including the NIST-recommended elliptic curves. It occupies 618 slices and 607 slices in Xilinx Spartan-6 and Virtex-7 FPGA platform, computes in$10.6\ \mu \mathrm{s}$and 6.45 over the prime filed P-256, at a maximum operating frequency of 33.76 MHz and 55.49 MHz. It occupies 23997 GE and 28471 GE, computes in$1.25\ \mu \mathrm{s}$and$2.43\ \mu \mathrm{s}$over the prime fields P-256 at a maximum operating frequency of 285.71 MHz and 147.06 MHZ, respectively for TSMC 90nm and 180nm technology node implementation.

Obtaining accurate assessments of blood glucose level (BGL) by any means that can be recorded easily in real-time has been a trending research focus area in recent years. Indeed, BGL indicators can help identify health risks associated with diabetes mellitus or provide efficient assistance and monitoring to patients diagnosed with diabetic conditions. However, the conventional methods of measuring blood glucose level require an invasive blood sampling technique to analyze the proportion of glucose in blood components. This method causes discomfort and relatively bulky equipment to remain available as portable systems. In this work, we proposed a system that uses long-term recurrent convolutional networks (LRCN) using non-invasive biomedical signal recording to estimate the blood glucose level. The proposed LRCN is combined with a robust feature extraction mechanism and can benefit from the temporal sensitivity of long short-term memory, to find a mathematical relationship between a photoplethysmogram (PPG) and blood glucose levels. The proposed system achieved 4.7 and 11.146 as mean absolute error (MAE) and root mean squared error (RMSE), respectively, on the predicted BGL values in comparison with standard BGL invasive blood sample recordings device values.

An adaptive PUF source stabilization digital engine is proposed, applied to a symmetrical SR-latch structure for metastable PUF source, and implemented on TSMC 90nm process. In a global PUF system design, the stability of the PUF source directly affects the burden of error correction coding, as well as the required time and space resource consumption. According to the measurement and stability performance analysis of the PUF challenge and response results from 16 chips, although most of the PUF cells were having stable states, a non-negligible number of cells remained in oscillating states, in addition to major inter-chips differences for stability performances. Dark bit masking and Temporal Majority Voting(TMV) is a common and effective method to stabilize a PUF source but it involves a trade-off between stability and entropy loss. Stabilization with a fixed process design cannot achieve the best performance considering the large stability variations across different chips. We proposed an adaptive PUF stabilization processing engine that provides an enhanced TMV approach with the ability to stabilize the PUF source without reducing the expected number of PUF entropy. The PUF source raw bit error rate(BER) improved from 1.6e-2 to 1.7e-6 after stabilization.

This paper presents a wearable system able to transmit a real-time electrocardiogram (ECG) from a chest device to a photoplethysmogram (PPG) device on a wristband using human body communication (HBC). The proposed communication system was designed based on wet electrodes body channel measurements and was implemented using off-the-shelf components and conductive fabric rather than the original wet electrodes. This work attempts to build a bridge between standard surface potential monitoring and smart clothing technologies. The transmission of the ECG using the body as a transmission media from the chest to wrist reached an average accuracy of 97.1% tested for three typical cardiovascular monitoring positions. This work demonstrates a fully wearable HBC system that can be considered for smart clothing technology. The effective data transfer rate was 468kbps using on-off-keying (OOK) centered at 30MHz.

A human body communication system connecting a wearable electrocardiogram device and photoplethysmogram device system will be demonstrated. This live demonstration system is composed of two wearable sensors and real-time signals display on a laptop. During the live demonstration, the system will demonstrate the effective transmission of ECG data via a body communication link with a parallel Bluetooth comparison as reference. The PPG device system acts as body communication receiver and the final display will present sample-synchronized ECG and PPG signals creating a on-body sensors sub-network.

An AI-edge affective computing platform with wearable electroencephalogram, electrocardiogram, and photoplethys-mogram sensors will be demonstrated [1]. This live demonstration is composed of three physiological sensors, real-time displayed signals, and emotion classification results on a laptop. During the live demonstration, The visitor can monitor his/her emotion classification result every second and the physiological signals displayed on GUI on the laptop.

In this paper, we presented an affective computing engine using the Long-term Recurrent Convolutional Network (LRCN) on electroencephalogram (EEG) physiological signal with 8 emotion-related channels. LRCN was chosen as the emotional classifier because compared to the traditional CNN, it integrates memory units allowing the network to discard or update previous hidden states which are particularly adapted to explore the temporal emotional information in the EEG sequence data. To achieve a real-time AI-edge affective computing system, the LRCN model was implemented on a 16nm Fin-FET technology chip. The core area and total power consumption of the LRCN chip are respectively 1.13×1.14 mm2and 48.24 mW. The computation time was 1.9µs and met the requirements to inference every sample. The training process cost 5.5µs per sample on clock frequency 125Hz which was more than 20 times faster than 128μ achieved with GeForce GTX 1080 Ti using python. The proposed model was evaluated on 52 subjects with cross-subject validation and achieved average accuracy of 88.34%, and 75.92% for respectively 2-class, 3-class.

Abstract Social computing is a disruptive technology that is changing how we do business and building the enterprises. Mining consumer insights and consumer segmentation are the new drivers that are likely to be the cornerstone of developing new service innovations and social interactions. This special issue was designed to stimulate research on the data mining tools and methods for social computing. In this editorial, we are outlining the broad research framework on social computing, including the papers in this special issue and areas for future research.

As blockchain technology is becoming a driving force in the global economy, it is also gaining critical acclaim in the e-commerce industry. Both the blockchain and e-commerce are inseparable as they involve transactions. Blockchain protect transactions and e-commerce activities rely on them. Blockchain technology enables a decentralized marketplace to support important business activities like secure payments, managing the supply chain and reducing the fraud to mention few. In this special issue editorial we are introducing 11 research articles in this hot area of research that were selected by our reviewers from over than 250 submissions. As blockchain technology is becoming a driving force in the global economy, it is also gaining critical acclaim in the e-commerce industry. Both the blockchain and e-commerce are inseparable as they involve transactions. Blockchain protect transactions and e-commerce activities rely on them. Blockchain technology enables a decentralized marketplace to support important business activities like secure payments, managing the supply chain and reducing the fraud to mention few. In this special issue editorial we are introducing 11 research articles in this hot area of research that were selected by our reviewers from over than 250 submissions.

In this paper, we developed and integrated an AI-edge emotion recognition platform using multiple wearable physiological signals sensors: Electroencephalogram (EEG), electrocardiogram (ECG), and photoplethysmogram (PPG) sensors. The emotion recognition platform used two combined machine learning approaches based on two systems input and preprocessing: An EEG-based emotion recognition system and an ECG/PPG-based system. The EEG-based system is a convolution neural network (CNN) that classifies three emotions, happiness, anger and sadness. The inputs of the CNN are extracted from the EEG signals using short-time Fourier transform (STFT), and the average accuracy for a subject-independent classification reached 76.94%. The ECG/PPG-based system used a similar CNN with an extracted features vector as input. The subject-dependent ECG/PPG classification system reached an average accuracy of 76.8%. The proposed system was integrated using the RISC-V processor and FPGA platforms to implement realtime monitoring and classification on edge. A 3-to-1 Bluetooth piconet was deployed to transmit all physiological signals on a single platform access point and to make use of low power wireless technologies.

This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six frequency bands (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose a phone number by gazing at the display interface. This proposed EEG system has been implemented in Field-Programmable Gate Arrays (FPGA), and shows high accuracy, high integration density, and low cost. These features are meaningful for implementing a real-time SSVEP-based BCI.

This paper presents a highly integrated multiprocessor system-on-chip (SoC) design, enabling real-time processing of multi-biomedical signals in a wireless bedside monitoring system. This system includes a real-time online recursive independent component analysis (ORICA) processor to automatically remove brain electroencephalogram (EEG) artifacts signals, a heart rate variability (HRV) analysis processor for monitoring electrocardiogram (ECG) signals, and a basic biomedical signal processor for monitoring common physiological data such as oxygen saturation, blood pressure, or body temperature. The multiprocessor chip is fabricated using TSMC 90 nm CMOS technology, and occupies a core area of 1,600 × 1,600 um2. Simulated power consumption is 15.89 mW under the conditions of 1.0V core supply voltage and 64 MHz clock operation frequency.

This paper presents a VLSI design of singular value decomposition (SVD) processor used in real-time independent component analysis (ICA) computation for multi-channel electroencephalography (EEG) system. EEG signals are easily influenced by other artifacts. To acquire artifact free EEG signals, ICA is a popular method for artifact removal. Results obtained after the pre-processing of ICA are often used for further applications such as brain computer interfaces (BCIs). In order to improve the feasibility and convenience of BCIs, a real-time ICA pre-processing is required. Because SVD is used frequently in computations of ICA, a SVD processor used for real-time ICA computation is essential. This paper aims to develop a custom SVD for multi-channel EEG systems based on ICA. During the ICA process, the proposed processor aims to solve the inverse and inverse square root matrices in real time. And the processor obtains a highly accurate result since a novel design concept for renewing data flow and parallel data processing are provided in this research. This processor is developed with TSMC 90nm CMOS technology in an 8-channel EEG system. The performance of the proposed SVD is also provided with the processing result of the EEG system.

In recent years, many studies of 2-D oxygen saturation distribution reconstruction have provided easy access to human brain activity regions. However, only a few research focus on the home health care system using this technique. In this paper, we proposed a portable, low cost and real-time distribution reconstruction system of oxygen saturation in 2-D to make diagnosis at home possible. The system has been implemented in hardware as an oxygen saturation processor and verified on Field Programmable Gate Array (FPGA). Furthermore, we also introduce an image post processing unit to enhance the reconstruction result. Finally, we show that our system can recognize the variation of oxygen saturation region with high precision in detection tissue.

It is known that ECG signal are strongly affected by the chest motion of respiration. We utilize this property and derive a respiration related signal with respect to the change of R wave area, and then match the derived signal to the time axis. We discovered that during the apnea section, a lower frequency component compared to the respiration frequency is observed. With the presence and absence of this lower frequency modulation on the ECG signal, we propose a real-time detection method to differentiate the apnea section and normal breathing section in the duration of sleep.

Exchange of medical information between hospitals is an essential part for medical treatments. In addition, security issues relating to electronic exchanges of information should also be concerned to protect the patient's privacy and to help the treatments. In cooperation with the Health Level seven (HL7) standard, we employ reversible data hiding to further assist reducing the human errors during the exchange of information delivery. Reversible data hiding has attracted more and more attention in both researches and applications. We consider hiding part of the HL7 information into medical images at the encoder, and at the decoder, both the original image and HL7 information can be perfectly recovered. Simulation results demonstrate the superiority over existing schemes, and the effectiveness for practical applications.

This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different training window sizes. The proposed low power ICA processor can separate EEG and mixed EEG-like super-Gaussian signals in real time. The chip can be operated at up to 60MHz working frequency and a maximum sampling rate of 9.394 KHz for EEG signals. The power consumption of this chip is 0.690 mW during training under the condition of 0.9V supply voltage and 10 MHz operating frequency using UMC 90nm High-Vt CMOS technology. The total chip area is 1230 × 1230 μm1.

In this paper, a highly-integrated multiprocessor chip design enabling the real-time processing of biomedical signals in portable brain-heart monitoring systems is presented. The architecture comprises a novel diffuse optical tomography (DOT) processor for taking brain imaging, an independent component analysis (ICA) processor for removing artifacts of brain electroencephalogram (EEG) signals, and a heart rate variability (HRV) analysis processor for monitoring heart electrocardiogram (ECG) signals. The multiprocessor chip implemented in 65nm CMOS technology comprises 368k gates and occupies a core area of 462k μm2. Simulated power consumption using a full operation test case reports 3.6mW under the condition of 1.0V core supply voltage and 24MHz clock operating frequency.

In this paper, an efficient sphere decoding algorithm (SDA) applied to solve the inter-symbol-interference (ISI) data detection problem is proposed. This proposed algorithm takes advantages of the SDA to obtain the solution close to ML solution with the simplified K-best tree search method for the ISI data detection under ISI effect. Compared with the frequency-domain MMSE or Zero-Forcing equalization techniques for SCBT (Single-Carrier Block Transmission) systems, this algorithm can perform at least 1.5dB better than frequency- domain equalizers under the environment of randomly generated channel impulse responses.

Reversible data hiding has attracted more and more attention in both researches and applications. It can be categorized into two branches, one is histogram-based scheme, and the other is performed by adjusting the difference between adjacent pixel pairs. We consider the advantages of both methods and integrate them altogether, and propose the histogram-based difference expansion scheme for reversible data hiding. Simulation results demonstrate the superiority and ease of implementation of the proposed algorithm.

An innovative multi-mode depth buffer compression algorithm has been developed for 3D graphics system. It adaptively compresses the depth buffer data according to different scene changes by employing 19 compression modes generated from three compression algorithms including DDPCM, HA, and general DDPCM. Furthermore, this novel algorithm supports one-plane and two-plane compression modes and manipulates break points more efficiently. For 8x8 tile size and 16-bit depth values, the proposed multi-mode algorithm can achieve 1.91:1 compression ratio on average and improve 76.9% and 39.4% compared with the HA and the DDPCM compression methods, respectively. The modified efficient depth buffer compression can achieve 10.56:1 and 7.76:1 compression ratio in one-plane mode and two-plane mode, respectively. The modified DDPCM can achieve 6.48:1 and 5.39:1 compression ratio in one-plane mode and two-plane mode, respectively.

In this paper, an intelligent surveillance system using sensor networks for monitoring active volcanoes has been presented. The authors combine sensor network system engineering with systems-on-chip implementation to develop a gigascale integrated surveillance system called sensor networks for active volcanoes (SNAV). The paper reports SNAV specific science-related requirements and system-level operations for this surveillance system. The paper also presents the SNAV system-on-chip implementation. The success of this work enables low-power, low-cost sensor networks for the intelligent surveillance systems

A CCSDS-compliant lossless data compressor core for space data and communication system-on-chip designs has been developed to meet the increasing strong demands on high-bandwidth high-speed space data systems. This data compressor core is based on CCSDS lossless data compression standard and designed with space-qualified 150-nm CMOS technology. It occupies a compact chip area of about 700/spl mu/m /spl times/ 700 /spl mu/m. The total power dissipation is 0.2 watts at a throughput rate of 66 Msamples/sec. This compressor core meets low-power, high-throughput, and user-transparent requirements and will be one of valuable silicon intellectual properties for developing next generation high-performance system-on-chip based space data and communication systems.

A low power smart vision system based on a large format (currently 1 k/spl times/1 k) active pixel sensor (APS) integrated with a programmable neural processor for fast vision applications is presented. The concept of building a low power smart vision system is demonstrated by a system design, which is composed with an APS sensor, a smart image window handler, and a neural processor. The paper also shows that it is feasible to put the whole smart vision system into a single MCM chip in a standard CMOS technology. This smart vision system on-a-chip can take the combined advantages of the optics and electronics to achieve ultra-high-speed smart sensory information processing and analysis at the focal plane. The proposed system will enable many applications including robotics and machine vision, guidance and navigation, automotive applications, and consumer electronics. Future applications will also include scientific sensors such as those suitable for highly integrated imaging systems used in NASA deep space and planetary spacecraft.

A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolation between the circuit-under-test and idle circuits.

A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital process for mixed-signal VLSI in a die size measuring 2.2 mm/spl times/2.2 mm.

A low power smart vision system based on a large format (currently 1 K/spl times/1 K) active pixel sensor (APS) integrated with a programmable neural processor for fast vision applications is presented. The concept of building a low power smart vision system is demonstrated by a system design which is composed with an APS sensor, a smart image window handler, and a neural processor. The paper also shows that it is feasible to put the whole smart vision system into a single chip in a standard CMOS technology. This smart vision system on-a-chip can take the combined advantages of the optics and electronics to achieve ultra-high-speed smart sensory information processing and analysis at the focal plane. The proposed system will enable many applications including robotics and machine vision, guidance and navigation, automotive applications, and consumer electronics. Future applications will also include scientific sensors such as those suitable for highly integrated imaging systems used in NASA deep space and planetary spacecraft.

In this paper, we describe current results from work in progress on the continued miniaturization of all spacecraft electronics into a single avionics system, using building-block elements. Each element is assumed to be a 'slice' within a stackable multichip module (MCM) 3D-architecture. The proposed architecture is new for the space community, but, is familiar to the commercial world. That is, we have proposed the use of only standard commercial interfaces for both the local (inter-slice) bus, inter-node system bus, and all the other interfaces for module testing and integration. Moreover, only commercially available programming languages, operating systems and software development environments are considered. The goal is to provide high levels of system reliability at a low cost. We plan to achieve this goal by applying hardware redundancy where necessary, and by maintaining a commercially compatible architecture that will achieve reliability through high volume production and mass usage. The first opportunity to validate the proposed spacecraft avionics system will be in July 1998 on-board the Deep-Space One asteroid-flyby mission. This will be the first in a series of high-tech missions within the New Millennium Program managed by the Jet propulsion Laboratory.

A smart-pixel cellular neural network with hardware annealing capability, digitally programmable synaptic weights, and multisensor parallel interface has been under development for advanced space sensor applications. The smart-pixel CNN architecture is a programmable multi-dimensional array of optoelectronic neurons which are locally connected with their local neurons and associated active-pixel sensors. Integration of the neuroprocessor in each processor node of a scalable multiprocessor system offers orders-of-magnitude computing performance enhancements for on-board real-time intelligent multisensor processing and control tasks of advanced small satellites. The smart-pixel CNN operation theory, architecture, design and implementation, and system applications are investigated in detail. The VLSI implementation feasibility was illustrated by a prototype smart-pixel 5/spl times/5-neuroprocessor array chip of active dimensions 1380 /spl mu/m/spl times/746 /spl mu/m in a 2-/spl mu/m CMOS technology.

A cellular neural network (CNN) is a locally connected, massively paralleled computing system with simple synaptic operators so that it is very suitable for VLSI implementation in real-time, high-speed applications. VLSI architecture of a continuous-time shift-invariant CNN with digitally-programmable operators and optical inputs is proposed. Circuits with annealing ability are included to achieve optimal solutions for many selected applications.

A self-organization neural network architecture is used to implement vector quantization for image compression. A modified self-organization algorithm, which is based on the frequency-sensitive cost function and centroid learning rule, is utilized to construct the codebooks. Performances of this frequency-sensitive self-organization network and a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. Good adaptivity for different statistics of source data can also be achieved.>

A high-speed image compression VLSI processor based on the systolic architecture of difference-codebook binary tree-searched vector quantization has been developed to meet the increasing demands on large-volume data communication and storage requirements. Simulation results show that this design is applicable to many types of image data and capable of producing good reconstructed data quality at high compression ratios. Various design aspects of the binary tree-searched vector quantizer including the algorithm, architecture, and detailed functional design are thoroughly investigated for VLSI implementation. An 8-level difference-codebook binary tree-searched vector quantizer can be implemented on a custom VLSI chip that includes a systolic array of eight identical processors and a hierarchical memory of eight subcodebook memory banks. The total transistor count is about 300000 and the die size is about 8.67/spl times/7.72 mm/sup 2/ in a 1.0 /spl mu/m CMOS technology. The throughput rate of this high-speed VLSI compression system is approximately 25 Mpixels per second and its equivalent computation power is 600 million instructions per second.>

The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme. To maintain strong signal strength over the whole system, global data communication between the host computer and neuroprocessors is carried out in a digital common bus. A mixed-signal very large scale integration (VLSI) neural chip that includes multiple neuroprocessors for fast video motion detection has been developed. Measured results of the programmable synapse, and winner-takes-all circuitry are presented. Based on the measurement data, system-level analysis on a sequence of real-world images was conducted.

A self-organization neural network architecture is used to implement the vector quantizer for image compression. A modified self-organization algorithm, which is based on the frequency upper-threshold and centroid learning rule, is utilized for constructing the codebooks. The performances of the self-organization network and the conventional algorithm for vector quantization are compared. This algorithm yields near-optimal results and is computationally efficient. The self-organization network approach is suitable for adaptive vector quantizers. The self-organization network approach uses massively parallel computing structures and is very promising for VLSI implementation.>

An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mmx6.8 mm in a 2.0 mum scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented.

A trainable VLSI neuroprocessor for adaptive vector quantization based upon the frequency-sensitive competitive learning algorithm has been developed for high-speed high-ratio image compression applications. Simulation results show that such an algorithm is capable of producing good-quality reconstructed image at compression ratios of more than 20. This design includes a fully parallel vector quantizer and a pipelined codebook generator which obtains a time complexity O(1) for each quantization vector. A 5*5-dimensional vector quantizer prototype chip has been designed, fabricated and tested. It contains 64 inner-product neural units and an extendable winner-take-all block. This mixed-signal chip occupies a compact Si area of 4.6*6.8 mm/sup 2/ in 2.0- mu m scalable CMOS technology.>

A locally connected multi-layer stochastic neural network and its associated VLSI array neuroprocessors have been developed for high-performance image flow computing systems. An extendable VLSI neural chip has been designed with a silicon area of 4.6*6.8 mm/sup 2/ in a MOSIS 2 mu m scalable CMOS process. The mixed analog-digital design techniques are utilized to achieve compact and programmable synapses with gain-adjustable neurons and winner-take-all cells for massively parallel neural computation. Hardware annealing through the control of the neurons' gain helps to efficiently search the optimal solutions. Computing of image flow using one 2 mu m 72-neuron neural chip can be accelerated by a factor of 187 more than a Sun-4/260 workstation. Real-time image flow processing on industrial images is practical using an extended array of VLSI neural chips. Actual examples on moving trucks are presented.>

An adaptive VLSI neuroprocessor based on vector quantization algorithm has been developed for real-time high-ratio image compression applications. This VLSI neural-network-based vector quantization (NNVQ) module combines a fully parallel vector quantizer with a pipelined codebook generator for a broad area of data compression applications. The NNVQ module is capable of producing good-quality reconstructed data at high compression ratios more than 20. The vector quantizer chip has been designed, fabricated, and tested. It contains 64 inner-product neural units and a high-speed extendable winner-take-all block. This mixed-signal chip occupies a compact silicon area of 4.6*6.8 mm/sup 2/ in a 2.0- mu m scalable CMOS technology. The throughput rate of the 2- mu m NNVQ module is 2 million vectors per second and its equivalent computation power is 3.33 billion connections per second.>

The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2- mu m CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.>