PICO. A prefix, a name, and an HP Labs project that began in 1995. PICO stood for “Program In, Chip Out”.

FPGAs provide significant advantages in throughput, latency, and energy efficiency for implementing low-latency, compute-intensive applications when compared to general-purpose CPUs and GPUs. Over the last decade, FPGAs have evolved into highly configurable SoCs with on-chip CPUs, domain-specific programmable accelerators, and flexible connectivity options. Recently, Xilinx introduced a new heterogeneous compute architecture, the Adaptive Compute Acceleration Platform (ACAP), with significantly more flexibility and performance to address an evolving set of new applications such as machine learning. This advancement on the device side is accompanied by similar advances on higher-level programming approaches to make FPGAs and ACAPs significantly easy to use for a wide range of applications. Xilinx Vitis Unified Software Platform is a comprehensive development environment to build and seamlessly deploy accelerated applications on Xilinx platforms including Alveo cards, FPGA-instances in the cloud, and embedded platforms. It addresses the three major industry trends: the need for heterogenous computing, applications that span cloud to edge to end-point, and AI proliferation. Vitis supports application programming using C, C++ and OpenCL, and it enables the development of large-scale data processing and machine learning applications using familiar, higher-level frameworks such as TensorFlow and SPARK. To facilitate communication between the host application and accelerators, Xilinx Runtime library (XRT) provides APIs for accelerator life-cycle management, accelerator execution management, memory allocation, and data communication between the host application and accelerators. In addition, a rich set of performance-optimized, open-source libraries significantly ease the application development. Vitis AI, an integral part of Vitis, enables AI inference acceleration on Xilinx platforms. It supports industry's leading deep learning frameworks like Tensorflow and Caffe, and offers a comprehensive suite of tools and APIs to prune, quantize, optimize, and compile pre-trained models to achieve the highest AI inference performance on Xilinx platforms. This talk provides an overview of Vitis and Vitis AI development environments.

Zynq-7000 All Programmable SoC and the new Zynq Ultrascale+ MPSoC provide proven alternatives to traditional domain-specific application SoCs and enable extensive system-level differentiation, integration and flexibility through hardware, software and I/O programmability.

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Designing compilers for Explicitly Parallel Instruction Computing (EPIC.) architectures presents challenges substantially different from those encountered in designing compilers for traditional sequential architectures. These challenges are addressed not only by employing new optimizations that are specific to EPIC, but also by employing new ways to architect compilers. EPIC architectures provide features that allow compilers to take a proactive role in exploiting instruction level parallelism. Compiler technology is intimately intertwined with the target processor architecture, and compiler architects must solve new analysis and optimization problems to achieve the highest levels of performance. When complex optimizations are uniformly applied to large applications, the resulting slow compile speeds are unacceptable. Demanding requirements to produce high-quality code at high compile speed shapes the fundamental structure of EPIC compilers.

The PICO-N system automatically synthesizes embedded nonprogrammable accelerators to be used as co-processors for functions expressed as loop nests in C. The output is synthesizable VHDL that defines the accelerator at the register transfer level (RTL). The system generates a synchronous array of customized VLIW (very-long instruction word) processors, their controller local memory, and interfaces. The system also modifies the user's application software to make use of the generated accelerator. The user indicates the throughput to be achieved by specifying the number of processors and their initiation interval. In experimental comparisons, PICO-N designs are slightly more costly than hand-designed accelerators with the same performance.

Meld scheduling melds the schedules of neighboring scheduling regions to respect latencies of operations issued in one region but completing after control transfers to the other. In contrast, conventional schedulers ignore latency constraints from other regions leading to potentially avoidable stalls in an interlocked (superscalar) machine or incorrect schedules for non-interlocked (VLIW) machines. Alternatively, schedulers that conservatively require all operations to complete before the branch rakes effect produce inefficient schedules. In this paper, we present general data structures for maintaining latency constraint information at region boundaries. We present a meld scheduling algorithm that generates latency constraints at the boundaries of scheduled regions and utilizes this information during the scheduling of other regions. We present a range of design options and describe the reasons behind our particular choices. We cover certain pitfalls and discuss how to develop an algorithm that addresses these issues. We evaluate the performance of meld scheduling on a range of noninterlocked machine models on a set of SPEC 92 and Unix benchmarks. We also investigate the sensitivity of the performance improvements due to changes in issue width and instruction latencies.

Scalar performance on processors with instruction level parallelism (ILP) is often limited by control and data dependences. This paper describes a family of compiler techniques, called critical path reduction (CPR) techniques, which reduce the length of critical paths through control and data dependences. Control CPR reduces the number of branches on the critical path and improves the performance of branch intensive codes on processors with inadequate branch throughput or excessive branch latency. Data CPR reduces the number of arithmetic operations on the critical path. Optimization and scheduling are adapted to support CPR.

The performance of applications executing on processors with instruction level parallelism is often limited by control and data dependences. Performance bottlenecks caused by dependences can frequently be eliminated through transformations which reduce the height of critical paths through the program. While height reduction techniques are not always helpful, their utility can be demonstrated in a broad range of important situations.