With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. Statistical design methods have been proposed in the past to model the impact of process variations. However, all the existing methods deal almost exclusively with modeling delay variations of logical gates or physical variations of interconnect wires. This paper proposes a method of analytically analyzing statistical behavior of multiple coupled interconnects with an uncertain signal arrival time at each interconnect input (aggressors and the victim). The method utilizes delay-change characteristics due to changes in relative arrival time between an aggressor and the victim. The results show that the proposed method is able to accurately predict delay variations through a coupled interconnect.

In order to improve the efficiency of behavioral model verification, it is important to determine the points of diminishing return for a given verification strategy. This paper compares the existing stopping rules and presents a new stopping rule based on static Bayesian technique. The new stopping rule was applied to verifying 14 complex VHDL models. We used the figure of merit to compare the efficiency of the stopping rules. The results in terms of coverage and verification time were shown to consistently outperform existing stopping rules.

A real-time algorithm and its VLSI implementation for edge linking is presented. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n+12 clock cycles, where n is the number of pixel columns in the image.