Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of generating test vectors is an active area of research. The simplest approach to parallelization of the test generation process is to simply divide the processing of the fault list across multiple processors, Each individual processor then performs the normal test generation process on its own portion of the fault list, typically without interaction with the other processors. The major drawback of this technique, called fault partitioning, is that the processors perform redundant work generating test vectors for faults covered by vectors generated on another processor. An earlier approach to reducing this redundant work involved transmitting generated test vectors among the processors and fault simulating them on each processor. This paper presents a comparison of the vector broadcasting approach with the simpler and more effective approach of fault broadcasting. In fault broadcasting, fault simulation is performed on the entire fault list on each processor. The resulting list of detected faults is then transmitted to all the other processors. The results show that this technique produces greater speedups and smaller test sets than the test vector broadcasting technique. Analytical models are developed which can be used to determine the cost of the various parts of the parallel ATPG algorithm. These models are validated using data from benchmark circuits.

Generation of test vectors for the VLSI devices used in contemporary digital system is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of finding test patterns is an active area of research. This paper presents an approach to parallelization of the test generation problem that is targeted to a network-of-workstations environment. The system is based upon partitioning of the fault list across multiple processors and includes enhancements designed to address the main drawbacks of this technique, namely unequal load balancing and generation of redundant vectors. The technique is generalized enough that it can be applied to any test generation system regardless of the ATPG or fault simulation algorithm employed. Results were gathered to determine the impact of workstation processing load and network communications load on the performance of the system.>

There are two important early stages in the design of complex systems: modeling of the system (operational) specification, and modeling of the system performance. A link between operation specification and performance modeling via VHDL (VHSIC hardware description language) is proposed, and it is shown by an example how the models can be made to interact, yielding a synergy leading to design efficiency and accuracy. The usefulness of such a link is justified by an example.>

The authors discuss methodologies and tools that allow a system to be analyzed using Petri nets or queuing models. Models at this level contain tokens rather than values, and the function of blocks remains undefined. Such analysis is performed early in the design process to evaluate overall system performance. Different methodologies and tools are available to allow design analysis and verification at interpreted levels through hardware design language (HDL) descriptions. Tokens are replaced with specific values for the representation of signals. The methodology presented allows the designer to create uninterpreted models in an environment already capable of interpreted modeling, the VHSIC hardware description language (VHDL). Uninterpreted modeling in an HDL is the first step in the creation of a continuous single-path design environment.>

Article Free Access Share on The design automation standards environment Author: R. Waxman Center for Semicustom Integrated Systems, School of Engineering and Applied Science, University of Virginia, Charlottesville, Virginia Center for Semicustom Integrated Systems, School of Engineering and Applied Science, University of Virginia, Charlottesville, VirginiaView Profile Authors Info & Claims DAC '87: Proceedings of the 24th ACM/IEEE Design Automation ConferenceOctober 1987 Pages 559–561https://doi.org/10.1145/37888.37971Published:01 October 1987Publication History 2citation134DownloadsMetricsTotal Citations2Total Downloads134Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The design processes are basically the same at all levels of applications - chip, board and system. Many businesses involved with design find themselves with a combination of manual methods and a variety of CA tools to accomplish different portions of this process. This implies that the information, or database, is found in a variety of media forms: on paper, on system A application B, on system C application D, etc. There is a tremendous need at this point in the CA tools industry's development to offer means by which these different parts of the design process, manual and automated, can transfer information intelligently between applications which may be resident on different platforms. Given sufficient time, and barring major differences between the various proponents, the ongoing development of industry-wide standards are possibly the solution to many of these issues.

The problem of adding k n-bit numbers, where k ≥ 3 is considered. A novel scheme for adding such k numbers is described. Applying the bit-partitioning technique so that each partition contains m bits of each of these k numbers, where m=[log2(k-1)] is an integer ≥ log2(k-1), the final sum can be obtained in m+1 addition cycles.