Declining birthrate and aging populations are progressing all over the world. This has led to labor shortage, making visual inspections more challenging in various industries. Recently, visual anomaly detection methods using deep learning have been proposed to solve these problems. However, they are computationally expensive and difficult to infer in real-time, even in a GPU environment. In addition, while they detect structural anomalies (e.g., scratches and stains), logical anomalies (e.g., mis-position and mis-number) cannot be detected. This work proposes an anomaly detection method to detect both structural and logical anomalies with high speed by improving Patch Core. The proposal applies self-attention mechanism for the intermediate layer of the pre-trained Convolutional Neural Networks(CNN) model. Self-attention mechanism enables the model to understand the relationships between image features and detect logical anomalies. In addition, the global and local features are extracted from the intermediate layer of the pretrained CNN model and stored in Separate Memory Bank (SMB). SMB leads to improving AUROC, which represents accuracy, by calculating features for each feature type. It also avoids unnecessary upsampling and reduces the dimensionality, thus improving inference speed. Experiments validate the proposed method and compare previous anomaly detection methods. Experiments evaluate the performance of the proposal for the CAD-SD dataset and MVTec LOCO dataset, which contains structural and logical anomalies. For Co-occurrence dataset, the experimental results show that the proposal achieves 98.5% (improving 2.2%) for AUROC and 16.1 (improving 66.6%) for FPS compared to the state-of-the-art method. Also, the experimental results show that the proposal achieves 82.8% (improving 0.9%) for MVTec-LOCO dataset. Hence, the proposal can contribute to the efficiency and automation of manufacturing, medical, and other fields.

We present a platform on all-programmable SoC for micro autonomous robots for probing, exploring, rescuing, etc. Contrast to challenges for auto drive cars having relatively rich power supply and high-performance computing platform, our challenge is to develop technologies for autonomous robots with tight restrictions on size, weight, and energy consumption. We utilize all-programmable SoCs for the purpose and develop a system including camera interface, image processing, recognition, action planning, and motor control. The key techniques are to optimize the dataflow between software (and main memory) and hardware for efficiency and to adopt a standard stream interface in hardware modules for productivity. The system can be utilized as a common platform for micro autonomous robots. The system is implemented as a robot car named ZybotR2-Z2 and achieves 3 to 37 frame/sec image recognition and car control with single Zynq-7020 device.

The real-time detection of defects in Flat-Panel Displays (FPDs) is very important during the production stages. This paper describes the manner in which defects induced by bubbles are detected as fast as possible by using 4-stage image processing pipelines with 3-line buffers on a Field-Programmable Gate Array (FPGA). The image processing consists of reading a Time Delay Integration (TDI) image, Laplacian filtering, binarization, and labeling. TDI is applied to the initial image of the FPD to reduce noises induced when taking the FPD images. Laplacian filtering and binarization are used to detect the edges in the image, and labeling is used to number the objects in the image for defect detection. In the 4-stage pipelining, the first stage reads the TDI image from the Block Random Access Memory (BRAM), the second stage implements Laplacian filtering and binarization, the third stage implements labeling, and the final stage revises the labels and writes them into the BRAM. The target pixel and its eight surrounding neighbors are required during Laplacian filtering, and four neighbors are necessary during labeling. Thus, three line registers (3-line buffer) are used as a general pipeline register between two neighboring stages in our system. The pipelining system accesses these 3-line buffers and runs four image processing steps in parallel. Therefore, the system uses four different addresses to access the BRAM and the 3-line buffers. Further, to facilitate performance comparison, we implemented sequential image processing systems with 3-line buffers on FPGA and CPU software. The experiments reveal that Laplacian filtering, binarization, and labeling for FPD defect detection can be executed in less than 1 ms by using four-stage pipelining on an FPGA, which is 3.62 times faster than the sequential system and 158.7 times faster than the CPU software. The pipelining system is 28% larger as compared to the sequential system in terms of the size of the LUTs.

In this paper, a prototype implementation of stream- ing system that allows listening to and viewing multimedia contents using a mobile terminal, as part of our efforts toward realizing services linked with home networks and mobile net- works is presented. In our system, appliances are detected and connected to a mobile terminal by use of peer-to-peer (P2P) network based on the PUCC protocols, and they are controlled by use of P2P messages and IEEE1394 AV/C. Streaming is managed by a gateway on the P2P network, where multimedia contents are converted to another format suitable to be sent to mobile terminals. This prototype system successfully achieves video data streaming over two different networks by using P2P network which conceals the differences among the networks.

Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from memory bit upsets caused by charged particles in space that result in fatal system troubles.This paper proposes an autonomous repair mechanism against configuration upsets for fault-tolerant reconfigurable devices. In proposed architecture, devices consist of 'Autonomous-Repair Cells' with built-in (not reprogrammable) error recovery circuits. Each cell realizes a part of the system's functionality, and guarantees fault tolerance against upset of its own configuration memory. In this paper, four types of Autonomous-Repair Cells are designed and then average lifetime is analyzed. Two of cells are based on TMR (Triple Module Redundancy) and the others are based on EDAC (Error Detection and Correction). In a severe situation where a conventional reconfigurable device with 1Mbit configuration data can achieve only 1-minute average lifetime against configuration upsets, all proposed cells can achieve more than 100 years.

Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from configuration memory upsets caused by radiation in space. This paper proposes an architecture of a fault-tolerant reconfigurable device based on island-style FPGA. The device consists of "autonomous-repair cells" which repairs these upsets autonomously and dynamically. To determine the architecture, we analyze four autonomous repair techniques of the cell experimentally. Then, optimal autonomous repair techniques are applied to both of programmable logics and cell-to-cell routing resources. Through evaluation, we show that proposed device achieves more than 10 years average lifetime against configuration upsets even in a severe situation such as a satellite orbit

To cope with the recent mobile scenes where images are used aggressively, a novel rate control scheme is proposed. The proposed scheme, dedicated for JPEG2000 image coding, aims at achieving low computational cost and small working memory size while maintaining high image quality. By predicting the adequate number of coding passes and updating it adaptively in code-block coding, the proposed scheme reduces both computational cost and working memory size for bitstream buffering down to 29% and 13%, respectively.

A new approach for the minimum area floorplanning is proposed where the shape of every module can vary under the constraint of area and floorplan topology. Simulating the air-pressure mechanics, the algorithms iterate to improve the layout to decide the shapes and positions of modules. It is proved that the layout approaches the optimal layout each step by the measure of energy which is defined by the current layout. Experimental results showed very fast convergence. An extension to a more practical case with the aspect-ratio constraint is discussed.