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Lori M. Kaufman

dblp:31/3423 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 76% Parallel and multicore computing · 14% Hardware reliability and fault tolerance · 10%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault coverage
0.012002
Coverage Estimation Using Statistics of the Extremes for When Testing Reveals No Failures · IEEE Trans. Computers 2002
Electronic design automation
hardware verification and test
0.011996
An analysis of fault partitioned parallel test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Parallel and multicore computing
parallel algorithms
0.011996
An analysis of fault partitioned parallel test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › hardware verification and test › test generation
parallel test generation
0.011996
An analysis of fault partitioned parallel test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › hardware verification and test
test generation
0.011996
An analysis of fault partitioned parallel test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Hardware reliability and fault tolerance
fault injection
0.012002
Coverage Estimation Using Statistics of the Extremes for When Testing Reveals No Failures · IEEE Trans. Computers 2002

Methods — techniques the papers use, named apart from their topics

statistics of the extremes · 0.0fault simulation · 0.0analytical modeling · 0.0
YearPublicationVenuePosition
2002 Coverage Estimation Using Statistics of the Extremes for When Testing Reveals No Failures
abstract
The existing classes of fault coverage models require an a priori distribution for collected data in their analysis. Using these models, analyses can be performed using various assumed distributions. The assumed distributions may not accurately reflect the behavior of the collected data and, as a result, the coverage values predicted by the models may be inaccurate, especially if testing yields little or no failure data. Since the occurrence of an uncovered fault in an ultra-dependable system is a rare event, then statistics of the extremes can be used to quantify uncoverage estimates in such systems. Statistics of the extremes provides for an analysis of rare event data without requiring any a priori knowledge of its distribution. It classifies most distributions into one of three asymptotic families; that is, in the limit, most distributions converge to one of three forms. Using statistics of the extremes, a coverage model is developed for when testing reveals no failures. From this model, the number of fault injection experiments required to demonstrate that a desired coverage level can be met is derived, as is the probability that this coverage estimate can be met.
Lori M. Kaufman, Barry W. Johnson, Joanne Bechta Dugan
IEEE Trans. Computers1
1998 Using statistics of the extremes for software reliability analysis of safety critical systems
abstract
Software reliability models have been successfully applied to many industrial applications, but have the unfortunate drawback of requiring data from which one can formulate a model. The data used for these models frequently comes from pre-release testing and/or field experience, and is of sufficient quantity and quality for most large-scale commercial applications. Software which is developed for safety-critical applications is frequently unable to produce such data, for at least two reasons. First, the software is frequently one-of-a-kind, and second, it rarely fails. Safety-critical software is expected to pass every test, producing precious little failure data. "Statistics of the extremes" is a special branch of statistics developed for analysis of rare events. Where traditional statistical analysis uses the law of large numbers to provide information concerning points which are near the mean of the distribution, statistics of the extremes concentrates on the tails. Analysis of rare event data using statistics of the extremes does not require a-priori assumptions concerning the distributional form of the data, and thus provides an interesting alternative to traditional approaches. In this paper, we develop a software reliability model using statistics of the extremes, which is particularly applicable to safety-critical software systems.
Lori M. Kaufman, Joanne Bechta Dugan, Barry W. Johnson
ISSRE1
1996 An analysis of fault partitioned parallel test generation
abstract
Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of generating test vectors is an active area of research. The simplest approach to parallelization of the test generation process is to simply divide the processing of the fault list across multiple processors, Each individual processor then performs the normal test generation process on its own portion of the fault list, typically without interaction with the other processors. The major drawback of this technique, called fault partitioning, is that the processors perform redundant work generating test vectors for faults covered by vectors generated on another processor. An earlier approach to reducing this redundant work involved transmitting generated test vectors among the processors and fault simulating them on each processor. This paper presents a comparison of the vector broadcasting approach with the simpler and more effective approach of fault broadcasting. In fault broadcasting, fault simulation is performed on the entire fault list on each processor. The resulting list of detected faults is then transmitted to all the other processors. The results show that this technique produces greater speedups and smaller test sets than the test vector broadcasting technique. Analytical models are developed which can be used to determine the cost of the various parts of the parallel ATPG algorithm. These models are validated using data from benchmark circuits.
Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1993 Workstation Based Parallel Test Generation
abstract
Generation of test vectors for the VLSI devices used in contemporary digital system is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of finding test patterns is an active area of research. This paper presents an approach to parallelization of the test generation problem that is targeted to a network-of-workstations environment. The system is based upon partitioning of the fault list across multiple processors and includes enhancements designed to address the main drawbacks of this technique, namely unequal load balancing and generation of redundant vectors. The technique is generalized enough that it can be applied to any test generation system regardless of the ATPG or fault simulation algorithm employed. Results were gathered to determine the impact of workstation processing load and network communications load on the performance of the system.>
Robert H. Klenke, Lori M. Kaufman, James H. Aylor, Ronald Waxman, Padmini Narayan
ITC2