This paper presents a design for testability and minimum leakage pattern generation technique to reduce static power during test and burn-in for nanometer technologies. This technique transforms the minimum leakage pattern generation problem into a pseudo-Boolean optimization (PBO) problem. Nonlinear objective functions of leakage power are approximated by linear ones such that this problem can be solved efficiently by an existing PBO solver. A partitioning-based algorithm is applied for control point insertion and also CPU time reduction. Experimental results on the IEEE ISCAS'89 benchmark circuits using Taiwan Semiconductor Manufacturing Company 90-nm technology show that, for large circuits, the static power is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3600 s (without partition) to 83 s (with 64 partitions). This technique reduces the static power without changing the manufacturing process or library cells.

A diagnosis technique is presented to locate multiple timing faults in scan chains. Jump simulation is a novel parallel simulation technique which quickly searches for the upper and the lower bounds of every individual fault. The proposed technique takes into account the interaction of multiple faults so the diagnosis results are deterministic, not probabilistic. This technique is very useful in the production test environment because it requires only regular automated test pattern generator patterns, not specialized diagnosis patterns. Experiments on ISCAS'89 benchmark circuits show that this technique can successfully pinpoint almost every single one of 16 hold-time faults in a scan chain of more than 800 scan cells. The proposed technique is still effective when failure data are limited or faults are clustered.