A critical problem in pre-Silicon and post-Silicon validation of analog/mixed-signal circuits is to estimate the distribution of circuit performances, from which the probability of failure and parametric yield can be estimated at all circuit configurations and corners. With extremely small sample size, traditional estimators are only capable of achieving a very low confidence level, leading to either over-validation or under-validation. In this paper, we propose a multi-population moment estimation method that significantly improves estimation accuracy under small sample size. In fact, the proposed estimator is theoretically guaranteed to outperform usual moment estimators. The key idea is to exploit the fact that simulation and measurement data collected under different circuit configurations and corners can be correlated, and are conditionally independent. We exploit such correlation among different populations by employing a Bayesian framework, i.e., by learning a prior distribution and applying maximum a posteriori estimation using the prior. We apply the proposed method to several datasets including post-silicon measurements of a commercial high-speed I/O link, and demonstrate an average error reduction of up to 2x, which can be equivalently translated to significant reduction of validation time and cost.

This paper is intended to give a brief tutorial understanding of on-die power grid effects. Board, package and on-die power grids deliver power to a die having both global (full-die) as well as local (intra-die) transient effects. With a simple excitation model and a detailed die/package/board model, one can come to understand the dynamic effects occurring inside the die in terms of global and local voltage droop scenarios. These effects have been confirmed by measurements on-die. However, a simple excitation model is usually not representative of the worst-case transient scenarios causing the largest voltage droop. Any chip, especially a microprocessor, contains so many potential state transitions that it is not possible to simulate or enumerate all of them. A spectral-based learning and optimization method can alleviate this problem pre-silicon, while a micro-architectural based test generation scheme can help alleviate the problem post silicon.

Power grids with die-scale dimensions operate in a transient manner that is difficult to predict compared to larger power grids. Given a single excitation and a detailed model one can come to understand the dynamic effects occurring inside the die in terms of localized voltage droop scenarios. However, a major portion of understanding on-die power grids has to do with modeling the current stimulus pre-silicon for design purposes as well as generating a set of activities (via instructions) post-silicon in order to excite the worst case voltage droop. Any chip, especially a microprocessor, contains so many potential state transitions that it is not possible to simulate or enumerate all of them. A spectral-based learning and optimization method can alleviate this problem pre-silicon, while a micro-architectural based test generation scheme can help alleviate the problem post silicon.

Functional test content to screen for electrical marginalities during silicon validation are not generated with the goal of identifying speed-limiting paths, adversely affecting the quality and efficiency of validation. We propose a methodology to generate functional tests to excite pre-silicon timing-critical paths along with environmental effects such as voltage droop. These tests are to replace random/function-targeted content as the source for identifying speed failures during silicon validation. The effectiveness of this methodology is demonstrated through silicon experiments on a recent processor.

Summary form only given.The drive to low power regimes has highlighted the impact of power delivery dynamics on the operation and testing of the die. In normal functional mode, the transient draw of transistor currents will create scenarios that, via voltage droop, may impact the maximum operational frequency of the die. The same is true for functional testing. Even a need to replicate these effects for scan-based testing is not easily done without understanding both the dynamics of the power delivery as well as its impact on frequency during functional operation and functional testing. In this talk, power delivery dynamics will be discussed. Global and local voltage fluctuations will be mapped into the roughly four different kinds of voltage droops including the frequencies associated with each. It will be shown how decoupling capacitor placement either on a die or externally on the package will affect each of the kinds of voltage droops described. A description of the different die events, in either functional or scan mode, which can set up frequencies to impact each of the kinds of voltage droops, will be given. It will be shown that post-silicon functional speed-paths are often a clear function of the voltage droop dynamics. The second part of the problem consists in creating tests to excite the correct sequence of voltage droops to cause impact on the total droop seen by the transistors. We will discuss an early flow based on machine abstraction, charge assignment to reflect current draw, and charge sequence optimization to enable one to accomplish test-generation for droop post-silicon and the application of this flow on a major microprocessor. Post-silicon voltage measurements will be used to demonstrate the complexity needed to achieve a large droop impact in a short test which would be equivalent to running multiple functional tests.

As part of the design of large integrated circuits, one must verify that the power delivery network provides supply and ground voltages to the circuit that are within specified ranges. We introduce the concept of time-frequency description of circuit currents using wavelets, and use that to set up an optimization framework that finds the worst-case supply/ground voltage fluctuations. This framework allows for the quick determination of the impact of either the package or the die on the worst-case behavior, which enables their codesign. This approach has been applied to an industrial microprocessor design, resulting in realistic and nonobvious worst-case waveforms.

Variations in power supply voltage, which is a function of the power delivery network and dynamic current consumption, can affect circuit reliability. Much work has been done to understand power delivery robustness during both the design phase as well as the post-silicon validation phase. Methods applicable at the design phase typically synthesize worst-case current waveforms based on simple current constraints but fail to provide corresponding instruction streams due to their ignorance of the functional aspects of the machine and hence cannot be validated. Approaches used for post-silicon validation are not useful during design, and either rely heavily on available test content which can come from power, performance, or defect testing, and hence are limited in validation potential or employ manually-crafted tests aimed at power delivery, and hence are highly labor-intensive. In this paper, we provide a novel approach to construct processor current waveforms to induce significant droops while at the same time producing instruction streams to achieve those waveforms. We solve the pre-silicon current stimulus generation problem as an optimization problem. The modular framework in this paper utilizes microarchitectural information, current consumption estimates of fine-grained microarchitectural components and a pre-characterized power delivery network to obtain significant droop-inducing current waveforms. The paper further discusses techniques to convert operations associated with these generated waveforms to functional instruction streams. Silicon measurements of such tests run on an industrial microprocessor validate the approach.

In high performance designs, speed-limiting logic paths (speedpaths) impact the power/performance trade-off that is becoming critical in our low power regimes. Timing tools attempt to model and predict the delay of all the paths on a chip, which may be in the millions. These delay predictions often have a significant error and when silicon is measured there is a large variation of path delays as compared to the prediction of the tools. This variation may be caused by process, environmental or other effects that are often unpredictable. It is therefore desirable to use early silicon data to better predict and model potential speedpaths for subsequent silicon steppings. In this paper, we present a novel machine learning-based approach that uses a small number of identified speedpaths to predict a larger set of potential speedpaths, thus significantly enhancing the traditional timing prediction flows post-silicon. We demonstrate the feasibility of this approach and summarize our findings based on the analysis of silicon speedpaths from a 65nm P4 microprocessor.

Timing, test, reliability, and noise are modeled and abstracted in our design and verification flows. Specific EDA algorithms are then designed to work with these abstracted models, often in isolation of other effects. However, tighter design margins and higher reliability issues have increased the need for accurate models and algorithms. We propose utilizing silicon data to tune and improve the EDA tools and flows. In this paper we describe a silicon methodology to isolate silicon speedpath environments and feed these into a simulation framework to temporally and spatially isolate specific speedpaths in order to model and understand the real effects. This is done using accurate electrical speedpath modeling techniques which may be used to tune the accuracy and correlation of the design models. The effort required to distinguish the many different electrical effects will be outlined.

Current source models have emerged as a promising technique for reducing digital cell netlists to a simpler electrical model for use in timing and other applications. The Multiport Current Source Model (MCSM) is one of the most general models in this class, which has been shown to handle multiple electrical effects including multiple-input switching (MIS) events in timing. However, this new model is hampered by two major problems: port characterization runtime and accuracy across a range of complicated cells which are deployed in advanced microprocessor design such as complex combinational cells, muxes, and sequentials. In this paper we demonstrate a significant leap in modeling accuracy and characterization runtime over the MCSM model which effectively eliminates these remaining issues. The quality of the new approach is conclusively demonstrated on a comprehensive 45nm cell library currently in use. The new approach accurately models both complex combinational as well as, for the first time, sequential cells, and puts MCSMs on the path for next generation gate level electrical analysis.

The problem of multiple-input switching (MIS) has been mostly ignored by the timing CAD community. Not modeling MIS for timing can result in as much as 100% error in stage delay and slew calculation. The impact is especially severe on stages immediately after a bank of flops, where the inputs have a high probability of arriving simultaneously. Other problems such as modeling of interconnect loads, complex (nonlinear/non-monotonic) input waveforms, power-droop impact on cell delay, nonlinear input capacitances, delay variations due to cross-capacitance, etc. are also known sources of error. In this paper, we introduce the multi-port current source model (MCSM). MCSM can efficiently handle an arbitrary number of simultaneously switching inputs, including single-input switching (SIS). Moreover, MCSM is comprehensive in that other modeling problems associated with delay and noise computation are elegantly covered. We demonstrate the applicability of MCSM on a large 65 nm industrial test-case. For cells experiencing MIS, the model yields delay and slew-rate errors within ±5% for 88.3% and 93.0% of the cases, respectively. We also present data that show that MCSM is an effective receiver model which captures active loading effects without incurring significant additional error. MCSM makes combined cell-level timing, noise, and power analysis a possibility.

Much research has been done lately concerning analysis and optimization techniques for on-chip power grid networks.However, all of these approaches assume a particular model or behavior of the power delivery.In this paper, we describe the first detailed full-die dynamic model of an industrial microprocessor design, including package and non-uniform decap distribution.This model is justified from the ground up using a full-wave model and then increasingly larger but less detailed models with only the irrelevant elements removed.Using these models we show that there is little impact of on-die inductance in such a design, and that the package is critical to understanding resonant properties of the grid.We also show that transient effects are sensitive to non-uniform de-cap distribution and that locality is a tight function of frequency and of the package-die resonance, producing newly explained localized resonant effects.Specifically, all of these points have impact on what kind of analysis and optimization are required from CAD.

Full-chip power grid analysis is time consuming. Several techniques have been proposed to tackle the problem but typically they deal with the power grid as a whole or partition at unnatural boundaries. Using a locality effect under flip-chip packaging, we propose a natural partitioning approach based on overlapping power grid "shells". The technique makes more efficient any previous simulation techniques that are polynomial in grid size. It is also parallelizable and therefore extremely fast. Using complete partitions gives no loss of accuracy compared to a full matrix solution, while lesser partitions are conservative for droop and current. Results on a recent Pentium/spl reg/ microprocessor design show excellent speed and accuracy.

Transistor density on an integrated circuit continues to grow at an exponential rate. The associated complexities when applied to synthesis, layout, and timing analysis will become untenable within the framework of our current technological capabilities. This paper briefly outlines the problems facing the semiconductor industry early into the next decade. A SRC research thrust team consisting of members from various companies prioritized these problems and established a top ten list. This paper includes both problem descriptions as well as metrics to benchmark proposed solutions.

No abstract available.

Article Free Access Share on Efficient full-wave electromagnetic analysis via model-order reduction of fast integral transforms Authors: Joel R. Phillips MIT Department of EECS, Cambridge, MA MIT Department of EECS, Cambridge, MAView Profile , Eli Chiprout IBM Research Laboratory for Advanced Microprocessor Design, Austin, TX and IBM T. J. Watson Research Center, Yorktown Heights, NY IBM Research Laboratory for Advanced Microprocessor Design, Austin, TX and IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile , David D. Ling IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 377–382https://doi.org/10.1145/240518.240590Published:01 June 1996Publication History 39citation410DownloadsMetricsTotal Citations39Total Downloads410Last 12 Months11Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

With increasing miniaturization and operating speeds, loss of signal integrity due to physical interconnects represents a major performance limiting factor of chip-, board- or system-level design. Moment-matching techniques using Pade approximations have recently been applied to simulating modelled interconnect networks that include lossy coupled transmission lines and nonlinear terminations, giving a marked increase in efficiency over traditional simulation techniques. Nevertheless, moment-matching can be inaccurate in high-speed circuits due to critical properties of Pade approximations. Further, moment-generation for transmission line networks can be shown to have increasing numerical truncation error with higher order moments. These inaccuracies are reflected in both the frequency and transient response and there is no criterion for determining the limits of the error. In this paper, a multipoint moment-matching, or complex frequency hopping (CFH) technique is introduced which extracts accurate dominant poles of a linear subnetwork up to any predefined maximum frequency. The method generates a single transfer function for a large linear subnetwork and provides for a CPU/accuracy tradeoff. A new algorithm is also introduced for generating higher-order moments for transmission lines without incurring increasing truncation error. Several interconnect examples are considered which demonstrate the accuracy and efficiency in both the time and frequency domains of the new method.>

Article Free Access Share on Addressing high-speed interconnect issues in asymptotic waveform evaluation Authors: Eli Chiprout View Profile , Michel Nakhla View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 732–736https://doi.org/10.1145/157485.165110Published:01 July 1993Publication History 15citation254DownloadsMetricsTotal Citations15Total Downloads254Last 12 Months11Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

With ever increasing clock frequencies, accurate 3-D interconnect analysis in chips and packages is becoming a necessity. The retarded partial element equivalent circuit (rPEEC) method has been successfully applied to 3-D analysis but for large problems it becomes expensive in CPU and memory usage, and in time domain it sometimes has numerical problems. Complex frequency hopping (CFH), a new multi-point moment-matching technique, is expanded to handle retarded networks. CFH speeds up rPEEC frequency domain analysis of large frequency bands significantly. It also allows the efficient calculation of resonances and - most importantly - enables time domain modeling of rPEEC networks that have so far resisted analysis by any other method.

An efficient PLA crosspoint fault simulation algorithm is presented. Parallel Boolean vector operations on a bitwise representation of PLA faults replace set operations, leading to increasing efficiency as the PLA size grows. Experimental results demonstrate execution times averaging over 100% faster than PLATYPUS and almost two and a half orders of magnitude faster than the CHIEFS fault simulator.>