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Rudi J. Stans

dblp:31/3943 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault modeling
0.011991
A fault model for PLAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation
hardware verification and test
0.011991
A fault model for PLAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test › fault modeling
bridging fault
0.011991
A fault model for PLAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991

Methods — techniques the papers use, named apart from their topics

fault equivalence analysis · 0.0
YearPublicationVenuePosition
1991 A fault model for PLAs
abstract
A fault model for programmable logic arrays (PLAs) is discussed. This model maps realistic failures on four classes of faults: multiple stuck-at faults, multiple bridging faults, multiple crosspoint faults, and faults due to breaks in lines. It is shown that multiple stuck-at faults are equivalent to multiple crosspoint faults, multiple bridging faults are sub-equivalent to multiple crosspoint faults, and the set of patterns detecting multiple crosspoint faults is a subset of the set of patterns detecting multiple bridging faults. Hence, the set of patterns detecting multiple crosspoint faults also detects all multiple stuck-at faults and multiple bridging faults. This reduces the fault model for PLAs to two classes: multiple missing/extra crosspoint faults and multiple breaks.>
Michiel M. Ligthart, Rudi J. Stans
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2