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Wolfgang Hilberg

dblp:31/3951 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1966
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 77% Parallel and multicore computing · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › neuromorphic computing
associative memory		 0.011966
Simultaneous Multiple Response in Associative Memories and Readout of the Detector Matrix · IEEE Trans. Electron. Comput. 1966
Parallel and multicore computing
data permutation		 0.011966
Simultaneous Multiple Response in Associative Memories and Readout of the Detector Matrix · IEEE Trans. Electron. Comput. 1966

Methods — techniques the papers use, named apart from their topics

detector matrix readout · 0.0
YearPublicationVenuePosition
1966 Simultaneous Multiple Response in Associative Memories and Readout of the Detector Matrix
abstract
One of the time-consuming procedures in the operation of a digital computer arises from the need to rearrange portions of words during the execution of certain instructions. In a typical situation, the first stage of a complex control sequence is concerned with the disassembly of the word prior to sending the parts to registers for appropriate arithmetic treatment, and the last stage with reassembly into standard format. This overhead can be wasteful even when the interregister wiring has been chosen with a particular format in mind, and is accentuated whenever a nonstandard format is encountered.
Wolfgang Hilberg
 IEEE Trans. Electron. Comput.1