System security requires a solid foundation in both development and operation. During development, performance trade-offs result in security infrastructures that are more or less effective, but usually imperfect. Hence, during operation, runtime monitoring and anomaly detection continuously check for security issues.In this paper, we show how development and operation can be linked. We demonstrate how information and data from development and operation can be aggregated in a digital twin and/or digital thread which is used as the basis for runtime monitoring and anomaly detection. In particular, we address the trade-off between system security and performance in a concrete smart grid system.

Work-In-Progress Extended Abstract

International audience

International audience

The increasing need for validating heterogeneous Systems on Chip (SoC) before their costly fabrication gives rise to the development of numerous virtual prototyping tools, allowing not only the modeling of such systems, but also the simulation of the environment in which they will be embedded, including the crucial software. SoC designers indeed require flexible simulation frameworks that follow a component-based approach and that cover a wide field of physical/engineering disciplines... and no questions asked about the simulation intrinsics. Furthermore, for SMEs, laboratories, and enthusiastic makers with limited funding, the cost of these frameworks makes them unaffordable, especially when the target system hardware is supposed to be Open Source too. In this paper, we detail the principles of an Open Source SystemC Multi-Disciplinary Virtual Prototyping (SystemC MDVP) framework, which directly tackles with all these issues. We introduce the key concepts and methodology (relationships between Models of Computation and overall synchronization techniques) and insist on the importance of a “correct by construction” global model elaboration that allows to generate the hierarchy of solvers that make up the final simulator. We then show that a new Model of Computation, Electrical Network, has been added to SystemC MDVP to handle components with non-linear beahviors. The paper concludes with a quick presentation of the echOpen project which aims at designing a low-cost portable echography device modeled and simulated with the presented principles.

International audience

International audience

International audience

The design methodology of an embedded system should start with a system-level partitioning dividing functions into hardware and software. However, since this partitioning decision is taken at a high level of abstraction, we propose regularly validating the selected partitioning during software development. The paper introduces a new model-based engineering process with a supporting toolkit, first performing system-level partitioning, and then assessing the partitioning choices thus obtained at different levels of abstraction during software design. This assessment shall in particular validate the assumptions made on system-level (e.g. on cache miss rates) that cannot be precisely determined without low-level hardware model. High-level partitioning simulations/verification rely on custom model-checkers and abstract models of software and hardware, while low-level prototyping simulations rely on automatically generated C-POSIX software code executing on a cycle-precise virtual prototyping platform. An automotive case study on an automatic braking applicationillustrates our complete approach.

Telecommunication applications require an increasingly high throughput; their task graph often exhibits a high level of coarse grained parallelism. We extend the KPN model by multiple writers and readers and present the SystemC based co-design of a packet classification application on a multi processor system on chip.