We propose a 32-bit RISC-V processor supporting the RV32IC instruction set. The data path width of the core has been reduced to 16 bits to save power and silicon area. By that means, instructions are forced to complete in multiple cycles. Through optimizations taking advantage of instruction information and processed data a large number of unnecessary execution cycles can be pruned. Thereby, the throughput is significantly increased. Extensive evaluation of the optimizations validate the efficiency of the proposed microarchitecture. Moreover, a post-layout simulation of the placed-and-routed design confirms the benefits of the architecture, saving between 27% and 57% of energy compared to the Ibex processor on tested benchmarks.

This paper presents a residue amplifier scheme consisting of a high-speed current-steering (CS) digital-to-analog converter (DAC) and a wideband active back-biased open-loop amplifier. The proposed current-summing residue amplifier scheme utilizes a 4-bit CS-DAC converting the first-stage sub-ADC output, which is subtracted from the resampled input current generated by the transconductance of the amplifier providing a nominal voltage gain of 8. The residue amplifier takes advantage of several measures to enhance output bandwidth, gain and linearity, which are inductive shunt peaking, source degeneration and active body biasing. The proposed 4-bit DAC and residue amplifier are designed for an energy-efficient 10 GS/s 7-bit two-step flash ADC. The proposed ADC achieves an ENOB and SFDR of 6.57/5.83 bit and 48/47.7 dBc at Nyquist frequency respectively, at a sampling rate of 5/10 GS/s. The DAC and residue amplifier are realized in the 22nm SOI CMOS process and consume 10.8 mW and 39.3 mW from a single 1.2 V power supply.

This paper presents the design of a 128 GS/s 64x time-interleaved SAR ADC, featuring an ultra-wideband two-rank hierarchical track-and-hold architecture maintaining 62 GHz bandwidth in 22nm CMOS FD-SOI technology. To achieve both, high bandwidth and concurrently adequate sampling linearity, an inductively peaked input network and first-stage source follower with pseudo-differential gain coupling is used, taking advantage of a dual -0.5V and 0.9V power supply. The front-end T/H also utilizes a mix of static and dynamic body-biasing techniques enabled by the 22nm CMOS SOI technology to further improve the linearity and signal gain. Each second-level buffer drives four 6-bit asynchronous loop-unrolled SAR ADCs at a conversion rate of 2 GS/s, using speed-optimized dynamic logic cells and MDAC redundancy to fulfil the sampling speed requirements. Time-interleaving mismatch effects such as gain, offset and sample skew errors are calibrated off-chip. The total signal bandwidth across the input network, first-level buffer and T/H stage exceeds 62.2/53.9 GHz and the ADC achieves a SNDR of well above 35.5/32.3 dB up to 19.7 GHz as well as 31.7/28.6 dB up to Nyquist-frequency in TT/SS corner.

This paper presents the architecture and implementation of a low-noise sub-sampling phase-locked loop (SSPLL) for mm-wave frequencies. It leverages an LC oscillator with a novel resonator, a digital lock assist and frequency calibration system as well as a novel charge pump implementation. The charge pump eliminates the pulser and runs continuously, which significantly reduces its power consumption while maintaining equal noise performance. The calibration system solves the lock problem of the SSPLL by implementing a lock/frequency search to prevent non- and false-lock. The LC oscillator employs an optimized resonator which combines both the inductor and the capacitor on the same metal, resulting in a very high quality factor by eliminating the interconnect resistance within the resonator. The SSPLL was implemented and simulated in a 22-nm-FDSOI technology, alongside with measurement results of the LC oscillator, which was fabricated in the same technology.

This work presents a 16 GS/s voltage-to-time conversion sampler architecture reaching an SNDR of 35.9 dB with a bandwidth of 17 GHz. Operating from a single 0.7 V supply consuming 6 mW of power. The sampler inherently performs a voltage-to-time conversion, enabling the use of power-efficient time-to-digital converters for further processing. The design is based on a CMOS inverter delay which is modulated by the input signal. In addition to the low power usage, it features a high input impedance compared to a conventional sampler where the input capacitance is determined by the noise target. In this paper a nonlinearity model for this circuit is derived and a prototype is implemented in a 22 nm CMOS FDSOI. The entire design is evaluated through SPICE simulations of the extracted layout.

This paper presents an 11-bit 12GS/s 4x timeinterleaved beam-forming ADC for a 2x2 antenna array in a 22nm FDSOI CMOS process. The RF-input is buffered with a push-pull source-follower providing both high linearity and high-bandwidth. The receiver utilizes sample-based beam-forming with a true time-delay generated from a clock delay network with uniform 11.9ps time-steps. Thus, all inputs are sampled phase-aligned without any phase-shifter in the RF-path. A chargebased summation enables a low-power beam-forming functionality without any wave-length dependencies. The summed output is buffered by a push-pull back-end buffer with cascodes providing a high-linearity. In total, 24x 11-bit 500MS/s SAR subADCs digitize the summed output of the beam-former. Time-interleave sample-phase mismatch can be calibrated with a 30fs step-size. The ADC achieves a voltage gain of 8.55dB in steering direction. An overall SFDR and SNDR above 68dBc and 55dB respectively is achieved. Only a total of 99.5mW per antenna is drawn.

Whereas Automotive Ethernet Physical Layer (PHY) Integrated Circuits (ICs) are typically qualified to ensure Electrostatic Discharge (ESD) robustness, an in-vehicle system-level ESD robustness is feasible only if the interactions between the various system components upon an ESD event are comprehensively considered and characterized accordingly. For these characterizations, the system PHY Signal Integrity (SI) and ElectroMagnetic Compatibility (EMC) aspects are at the forefront to validate the technical feasibility of the Electronic Control Unit (ECU). Towards high-speed ECU Printed Circuit Board (PCB) design for 25GBASE-T1(25Gbps Automotive Ethernet), system SI retention and prevention of ElectroMagnetic Interference (EMI) become even more crucial. This primarily results from having higher signal bandwidth (i.e., Nyquist frequency) and faster signal rise/fall time. In this study a detailed ESD validation considering the two critical ESD current paths in an ECU PCB implementation for 25GBASE-T1 for both powered and unpowered systems is discussed. A 25GBASE-T1 ECU Media Dependent Interface (MDI) PCB design concept is manufactured and utilized as test boards. The ESD current characteristics through the PCB Shield-GND (SG) termination are investigated and characterized in detail. Furthermore, to investigate also potential sources of ESD based EMI, an approach to combat EMI coupling during an ESD event within the ECU SG discharge current path is proposed.

In this paper, a novel charge pump for sub-sampling phase-locked loops (SSPLLs) is presented. Contrary to the conventional charge pump, the proposed implementation eliminates the previously-required pulser. This is achieved by using all sample data from the ping-pong sub-sampling phase detector as opposed to only every second point, which enables the charge pump to run pseudo-continuous. This virtually raises the reference frequency by a factor of two, which is beneficial for the phase noise performance of the phase-locked loop while fulfilling the requirements for bandwidth of reference buffers, switches etc. Furthermore, eliminating the pulser enables a highly power-efficient charge pump design, leveraging higher SSPLL FoM. The proposed charge pump is implemented in a 22-nm fully-depleted silicon-on-insulator technology. The power and area consumption are reduced by roughly 80% and 55%, with similar effective gain, noise and offset performance to the conventional design.

This paper presents a 12-bit segmented digital-to-analog converter (DAC) with small size high linearity non-cascoded current cells. A pre-distortion calibration technique, using a low-complexity lookup table, is proposed to cancel the third order code-dependent nonlinearity induced by low output impedance of unary current cells. Based on a detailed mathematical analysis, the coefficients of the digital pre-filter are deducted. In addition, the body biasing technique in$22\text{FDX}$technology is employed to adaptively tune the back-gate voltage of each current source via an auxiliary DAC to reduce mismatch errors. The current-steering (CS) DAC achieves >74dBc spurious-free dynamic range (SFDR) and >11 effective number of bits (ENOB) over the entire Nyquist bandwidth at IGS/s and across process and temperature corners. The implementation enables a small area and compact layout of the unary cells, low-power consumption from a dual 0.8/1.2V power supply and a 1-Vppd output signal swing without the use of cascode structures.

One of the main objectives of deploying Shielded Twisted Pair (STP) cables for Automotive Ethernet communication channels is to prevent ElectroMagnetic Interferences (EMI) from coupling onto sensitive in-vehicle sub-systems. Aside from the fact that currently various in-vehicle Electronic Control Unit (ECU) Printed Circuit Board (PCB) shield-ground implementation concepts are being deployed, there are several uncertainties regarding the correlation between these implementation concepts and their impact on radiated emissions of a multi-Gigabit Ethernet communication channel. Based on a defined Point-to-Point (P2P) emulated multi-Gigabit Ethernet communication channel topology, this study first commences by characterizing the channel ElectroMagnetic radiated Emissions (EME). To rule out potential impact of varying STP cable types in terms of their specified frequency coverage and vendor, this study further investigates, compares, and characterizes radiated emissions based on two commonly used STP cable types. The Automotive Ethernet multi-Gigabit speed grades in question include the recently standardized IEEE 802.3ch 2.5Gbps (2.5GBASE-T1), 5Gbps (5GBASE-T1), and 10Gbps (10GBASE-T1). Subsequent sections of this study investigate and characterize sources of the measured radiated emissions in relation to ECU PCB shield-ground implementation. Through this study, the correlation between Radio Frequency (RF) characteristics of an ECU PCB shield-ground implementation and radiated emissions of an Automotive multi-Gigabit Ethernet channel is shown. Additionally, analysis and simulation approaches are defined on how the sources of multi-Gigabit channel EME can be investigated and traced within the ECU PCB shield-ground implementation.

Next-generation data centers demand higher bandwidth, generating interest in 224 Gbit/s wireline transceivers. This paper analyzes the performance of PAM-4/PAM-6/PAM-8 for a co-packaged optical link including different channel lengths at 224 Gbit/s with all transceiver blocks, DSP equalization, and NEXT/FEXT crosstalk. With a 32-tap FFE and 1-tap MLSE equalization, a SER−3is achievable for PAM-4/PAM-6 for a channel attenuation <13dB at 56 GHz. Furthermore, a detailed power analysis is done for the modulations including all relevant transceiver blocks.

This paper presents an overview of the main copper-based automotive Ethernet communication standards, with an emphasis on the existing P802.3ch IEEE standard covering 2.5- 10Gb/s as well as the future P802.3cy standard for up to 50Gb/s full duplex communication. The requirements and key challenges of the automotive physical layer (PHY) are discussed and a 9-bit source series terminated (SST) TX-DAC driver with added echo canceler is proposed for the transmitter. The fabricated TX solution is realized in 22nm FD-SOI technology, and is fully compliant with the P802.3ch standard, proving a lVppd PAM4 output signal, >0.95 RLM while operating up to 11. 2Gb/s. At Nyquist frequency the SFDR is better than 54. 4dBFS while consuming only 2mW/Gb/s per DAC. A bandwidth-extended TX architecture is implemented covering also the P802.3cy standard, which enables PAM-4 signaling up to 14GBaud achieving an SFDR and ENOB of 57. 8dB and 8.1 bit respectively at Nyquist rate.

Orthogonal frequency-division multiplexing (OFDM)-based radars require a high bandwidth for the digital-to-analog (DAC) and analog-to-digital (ADC) converters. Recent advancements in converter designs have pushed the available sampling speed well above 50GS/s. This allows OFDM-based radar waveforms with a high bandwidth to be sampled directly to the carrier frequency, reducing the number of building blocks in the transceiver chain. This paper proposes a CMOS based radar and communication transceiver system design which achieves a range resolution of 10cm and a velocity resolution of 0.55m/s. Utilizing digital I/Q mixing and directly sampling a 1.52GHz bandwidth OFDM-based radar signal halves the number of required data converters and can significantly reduce the I/Q imbalance.

This research work focuses on electrical investigations and characterization of the Automotive Ethernet channel for 25Gbps (25GBASE-T1). This characterization is performed with the aid of insertion loss ($\mathrm{S}_{\mathrm{DD}12}/\mathrm{S}_{\mathrm{DD}21}$) mixed-mode scattering parameters (S-parameters) which describe the transmitted signal electrical behavior within the Ethernet channel considering it’s coupled transmission line characteristics. This paper commences with an introductory background of this research topic. This is then followed with an overview of the Automotive Ethernet channel and components. A succeeding section addresses the various channel electrical characteristic parameters. With the aid of implemented multi-gigabit Ethernet test boards, to emulate an ECU-ECU communication system setup, the fourth section investigates and discusses insertion loss test bench measurements and simulations on channel segments (PCB, link segment) and complete single 25Gbps (25GBASE-T1) Ethernet channel. The investigations in this study deploy Shielded Twisted Pair (STP) cables of varying length and cable topologies as a physical transmission medium. Last section addresses the key takeaways of this paper and recommendations on subsequent analysis.

This paper presents the design of a subsampling wideband 500 MS/s 12 Bit successive-approximation-register (SAR) analog-to-digital converter (ADC) with sub-2 radix split- capacitor array (SCA). The presented ADC is designed as a sub-ADC for a sample-and-hold-less (SAH-less) 8 GS/s time-interleaved (TI) ADC. In addition to the required 16 ADC channels, two additional SAR lanes enable pseudorandom binary sequence (PRBS)-driven channel scrambling. A 1.81 radix is used to achieve 12 Bit settling accuracy withing 70 ps. Extra scaling capacitors in the SCA enable SAR reference voltage levels near the supply rails, significantly reducing the SCA switch sizes. The necessity of a comparator latch reset phase is eliminated at the cost of higher comparator power consumption by the adoption of a loop-unrolled comparator improving the SAR loop timing. Top-plate charge kickback into the input buffer, a challenge that occurs within TI ADCs, is largely eliminated by implementing an additional reset phase within the SAR algorithm and the use of a boosted input T-switch. SCA and time-interleaved channel mismatch effects are addressed by calibrating each sub-ADC to an extra reference-ADC. The industry grade ADC design, achieves a spurious free dynamic range (SFDR) of 72 dB and signal to noise and distortion ratio (SNDR) of 54 dB across the entire 4 GHz frequency range. Designed in a 28 nm CMOS process, each sub-ADC consumes 33 mW from 1.8 V and 1V. The input buffer frontend uses supply voltages of 2.5 V and -1.3 V. The overall power consumption of the overall TI ADC is 3 W.

This paper presents a 56 GHz Sub-Sampling Phase-Locked Loop (SSPLL) for an optical transceiver system. It employs an LC oscillator without frequency multiplier featuring a novel combined resonator for high purity signals, a differential track-and-hold with dummy samplers, a charge pump with feedback amplifiers and specialized input pairs for high voltage operation. The sub-sampling architecture allows for ultra-low phase noise at low offset frequencies, while far-out phase noise is minimized due to the used high-purity oscillator. The phase noise at an 1MHz amounts to - 127dBc/Hz, resulting in a total integrated jitter of 19 fs (range from 1 kHz to 1 GHz). This 56 GHz SSPLL enables next-generation wire-line optical communication standards with over 100Gbit/s.

This paper presents a wideband 12 Bit 8 GS/s time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC), featuring a sub-2 radix architecture with an overrange of 10% and randomized sampling with mismatch correction in a 28 nm CMOS technology. For this purpose, 18 500 MHz SAR-ADCs plus an additional reference ADC are interleaved. This topology enables a randomization approach, reducing mismatch related interleaving spurs. Furthermore, the additional reference ADC operating in parallel to the main ADC enables adaptive digital calibration to correct for static and time-interleaved mismatch effects. A wideband front-end features two subsequent push-pull buffer stages to achieve a high track- and-hold (T/H) bandwidth and high sampling linearity, while improving kickback related settling limitations. After calibration, the ADC achieves a signal to noise and distortion ratio (SNDR) of 56.8 dB and a spurious free dynamic range (SFDR) of 80 dBc applying a single full scale sine wave tone close to the Nyquist frequency of 4 GHz.

In this article, an overview of the most recent fully-depleted silicon on insulator technology (FD-SOI) design techniques in the field of mixed-signal circuits and systems are given. Cutting edge performance is achieved by using dynamic as well as static body-biasing techniques. 22FDX®is a 22nm CMOS FD-SOI technology providing both, a unique wide-band body-bias tuning range in conjunction with minimized parasitic device loads, due to the significant reduced pn junctions in the signal path. As a result, transistor transit frequencies exceeding 400GHz with improved linearity is achieved. With a linear threshold voltage sensitivity of around 75mV per Volt, 22FDX®gives designers a competitive additional degree of freedom. After introducing 22FDX®, a 5-bit 18.5GS/s flash ADC is presented utilizing body-biasing to generate accurate threshold voltage offsets within the comparators and thus omitting a power-hungry resistive ladder. Then, dynamic body-biasing is used for a 1.5GS/s track-and-hold circuit to improve the bandwidth while the leakage is reduced obtaining 80dBc SFDR up to the fourth Nyquist zone. Furthermore, a 26GHz ring oscillator is presented, which utilize the strong threshold voltage sensitivity to fully compensate corner dependency. Finally, a body-biasing controlled DAC linearization technique for multi-bit Sigma-Delta modulators enabling 90dBc SFDR, as well as a DAC driver termination impedance control for a 6GS/s 10-bit automotive Ethernet SST-DAC-Driver are presented.

Minimum operating power limits possible energy sources in IoT nodes. This paper considers dynamic logic circuits based on c-axis aligned crystalline indium-gallium-zinc-oxide FETs as a design style reducing the minimum operating power of digital systems. A method for ensuring timing and signal integrity and the integration into a standard-cell design flow is presented. Based on a generated logic library, a RISC-V CPU with an outstanding estimated minimum operating power of 6.0 pW is presented. This result shows that systems based on this logic family surpass comparable systems based on CMOS technologies in terms of minimum operating power.

This paper presents a calibration technique that corrects errors introduced by the current-steering feedback DAC within CT-SDMs. Thanks to the extensive and linear back-gate sensitivity on the threshold voltage, the 22FDX technology enables a full correction of the DAC cell errors by adaptively tuning the back-gate voltage of each current source via an auxiliary DAC (AUX-DAC). In contrast to state-of-the-art analog DAC error corrections, the proposed adaptive body-biasing correction places the AUX-DACs outside of the feedback loop. Hence, the statically operating AUX-DACs enable a highly area- and power-efficient DAC linearization technique. Based on a detailed feedback DAC mismatch analysis, the required AUX-DAC resolution and range is deducted. In addition, potential kickback from the feedback DAC to the AUX-DACs as well as the AUX-DAC noise contribution to the total modulator noise are discussed on schematic level. Eventually, extensive system-level simulations that model and compensate random DAC weight mismatch verify the presented theoretical analysis.

State of art deep neural network (DNN) models are both memory prohibitive and computationally intensive with millions of connections. Employing these models for an embedded mobile application is resource limited with large amount of power consumption and significant bandwidth requirement (to access the data from the external DRAM). In a custom FPGA hardware the bandwidth access from the DRAM is two to three times higher, compared to the MAC (Multiply-Accumulate) operation. In this paper, we propose a power efficient multi-bit neural network accelerator, where we employ the technique of truncating the partial sum (PSum) results from the previous layer before feeding it into the next layer. We demonstrate that, using our multi-bit accelerator, accuracy is maintained upto bit width of 12. The proposed truncation scheme has 50% power reduction and resource utilization was reduced by 16% for LUTs (Look-up tables), 9% for FFs (Flip-Flops), 19% for BRAMs (Block RAMs) and 7% for Digital Signal Processors (DSPs) when compared with the 32 bits architecture. A large network, AlexNet was used as a benchmark DNN model and Kintex-7 KC705 FPGA was used to test the architecture.

In this paper a novel sampler that performs beam-forming is introduced. Several parts of the receiver chain are combined into one compact sub-sampling beam-forming summation track and hold (SSBS-TH). It directly integrates a true time delay with a phase correct summation unit. Furthermore the proposed circuit includes the sampling capacitance of a time interleaved (TI) analog-to-digital converter (ADC). The SSBS-TH operates at 12 GS/s to enable wide-band operation and cover frequencies up to 6 GHz. Therefore it is suitable for software defined radio (SDR). An overall linearity of 56 dBc and a signal-to-noise ratio (SNR) above 52.8 dB is achieved.

This paper presents a novel concept for educating future nano- and microelectronic engineers and IC-designers. An educational model for the full spectrum of the microelectronics value chain is presented, as well as the successful implementation of this model in the authors' curriculum. Main intention of this model is that students develop their own integrated circuits (ICs) based on a SiGe-BiCMOS technology for mm-wave applications, simulate functionality of the complex ICs by dedicated software tools, get an insight of their production and conclude their work in a final verification and characterization of the ICs. Finally, this educational model serves the way from basic knowledge to application in the rapidly growing business of micro- and nanoelectronics.

This paper presents a flash ADC architecture employing a comparator well-body biasing technique to eliminate the classical differential-difference amplifier (DDA) as well as the power-hungry reference ladder to enable significant power savings. DDAs require two differential pairs, one for the actual input signal and the other for the reference voltage whereas the proposed comparator technique merely uses a single differential pair for the input signal reducing the power consumption of the power-hungry preamplifier by approx. 50%. Furthermore, the flash ADC reference levels of the presented flash ADC, are generated by altering the input transistor threshold voltages. The adopted 22nm FD-SOI technology provides a threshold voltage tuning gain of approx. 85mV/V. Using a 3V capacitive charge-pump, a nominal full-scale range of 500 mVppdis achieved. This way, the proposed method also eliminates comparator kickback and therewith the low impedance requirement to guarantee settling of the reference ladder. The adopted technology provides a strong isolation from the gate to the back-gate of the input devices. The proposed techniques are adopted in a 5-bit 18.5 GS/s flash ADC. The track-and-hold along with the isolating front-end input buffer provides 28 GHz input bandwidth. The front-end buffer and SC charge pump operate from a 1.5V power supply while all other building blocks (comparator and clock tree) operate from a 0.9V power supply. The total power consumption is 140mW including clock buffers. The ADC achieves a SNDR and SFDR of 31dB and 43 dBc and 28.5dB and 40 dBc respectively at low and Nyquist input frequencies.

This paper presents an approach to optimally place noise coupling transfer functions (NCFs) zeros across the passband using oversampled analog-to-digital converters (ADCs). In addition, the presented optimization method is extended to account for and ultimately compensate NCF coefficient mismatch effects just using a single parameter only. As a result, NCF coefficient matching requirements are significantly relaxed enabling the robust design of accurate wideband oversampled data converters. The proposed technique is applied to two different ΣΔ ADCs both incorporating a second-order NCFs. For both ADCs, the optimal NCF zero placement is analytically calculated and verified through simulations. NCF coefficient mismatch simulations with the proposed single parameter compensation enabled, reveal a relaxed NCF coefficient matching requirement by a factor of 4× with only minor quantization noise penalties. Hence, the (analog) NCF filter area largely shrinks in size enabling ultra-compact oversampled ADCs.

This paper presents the estimation and digital correction of time-variant nonlinear errors introduced by the feedback DAC used within CT ΣΔ-ADCs. State-of-the-art digital foreground and background error estimations only account for static errors. Based on a detailed nonlinear channel analysis, a compact algorithm using pseudo random noise for estimating time-variant nonlinear errors is proposed. Comparison with a state of the art time-invariant estimation through extensive CT ΣΔ-ADCs simulations show outstanding error estimation and correction performance.

In this paper the design and non-linearity analysis of a 10-bit 1.6 GS/s source series terminated digital analog converter operating from a single 1.8 V power supply is presented. The DAC unit cell architecture is optimized for both high linearity and minimum crow-bar current. The latter one is particularly important to enable the use of inexpensive packaging technology like bondwire packages, which possess significant supply impedance. Finally, based on upper mentioned non-linearity analysis a 3bit auxiliary DAC is proposed, to improve the DAC integral non-linearity to below 0.15 LSB. Furthermore, the bondwire and DAC power supply impedance is accurately extracted enabling an optimum on-chip power supply decoupling strategy, to maximize the overall 1.6 GS/s DAC linearity performance.

This paper presents a calibration method that digitally compensates both static as well as time-variant non-linear errors introduced by feedback DACs used within CT ΣΔ-ADCs. State-of-the-art digital foreground and background DAC correction methods so far only consider static DAC errors preventing from realizing high linear CT ΣΔ-ADCs. Based on a detailed DAC non-linear inter-symbol interference analysis, the mathematical DAC model is extended and a correction method is proposed canceling static and time-variant DAC errors. Extensive CT ΣΔ-ADC simulations reveal an outstanding error compensation performance compared to state-of-the-art methods, enabling power-efficient realizations of high resolution CT ΣΔ modulators.

This paper presents a 40 Gbps micro-ring modulator driver which is designed in 130-nm SiGe technology. The proposed driver IC is optimized for a 2 Vppd output signal swing required for the optical modulator or 1 Vppd if terminated by 50 ohm. The power consumption is only 90 mW operated from a 2.5 V supply voltage. The inductor-less driver architecture consists of a fix-biased cascode topology with capacitive degeneration to improve the bandwidth and output voltage swing while minimizing the number of buffer stage to save power. The silicon area efficient driver occupies only 0.04 mm2. Simulation results exhibit a differential gain of 16 dB over 35 GHz. To the best knowledge of the authors, this driver represents the fastest micro-ring modulator driver IC with low transmitter FOM of only 1.12 pJ/(bit*V).

A decaying pulse shape DAC architecture for continuous-time (CT) SigmaDelta modulators is introduced. The DAC reduces the clock jitter sensitivity while putting only moderate design constrains on the respective integrators. The impact of clock jitter on the entire SigmaDelta modulator is computed and verified by electrical and behavioral simulations. In order to illustrate also the low-power benefits, the required integrator gain-bandwidth is evaluated and the obtained results are compared with corresponding simulation results. The DAC is implemented in a 1.8V 0.18mum CMOS process operating at a sampling frequency of fS=200MHz. The effect of process corners, supply voltage and temperature (PVT) is illustrated. Finally, various design constrains are discussed

This paper describes a new delay locked loop (DLL) architecture with infinite-skew tracking range. This is accomplished by two inverse operating delay lines, which work in a ping-pong fashion. Only a small number of delay elements are required, leading to a low delay gain and resulting in improved jitter performance compared to state of-the-art DLLs. The architecture has simple control, inherent start-up initialization, and good noise performance. The architecture is applicable for very wide frequency range while retaining good stability. It is also physically small. This architecture was designed in CMOS18 (0.18 mum) process for 1.6 Gb/s operation

This paper presents a design strategy for low-voltage low-power /spl Sigma//spl Delta/ analog-to-digital (A/D) converter using a continuous-time (CT) lowpass loop filter. An improved method is used to find the optimal /spl Sigma//spl Delta/ modulator implementation with respect to a minimal power consumption on the one hand and to fulfil a rapid prototyping approach on the other hand. The influence of the low supply voltage as well as circuit nonidealities on the overall /spl Sigma//spl Delta/ modulator is determined and verified by behavioral simulations. Transistor-level simulation results of a 1.5 V CT /spl Sigma//spl Delta/ A/D converter show a 75 dB dynamic range in a bandwidth of 25 kHz.

This paper presents the design of a 3rd-order lowpass SΔg-to-digital (A/D) converter using a continuous-time(CT) loopfilter. The loopfilter has been implemented by using active RC-integrators. The influence of the low supply voltage on the building blocks such as the amplifier and the common mode feedback as well as on the overall SDΔ A/D converter show a 75 dB dynamic range in a bandwidth of 25kHz. The expected power consumption is less than 300μW.