The IoT/M2M service providers need security mechanisms to avoid illegal usage of the service. Normally, this can be accomplished by using the certificate to authenticate the device before providing the service. In this paper, we consider the situation where a malicious user attempts to pay only for the service of a device but deploy the same certificate for many other devices to access the service illegally. To address this problem of duplicate certificates, we design two prevention mechanisms on top of the security framework defined in the oneM2M standard. Furthermore, we implement these two protection mechanisms on the OM2M platform and evaluate them in terms of their cost and performance in order to find the most suitable one for service providers.

This paper presents an inductive intrinsic parasitic feedback technique to enhance the circuit bandwidth of the electro-absorption/Mach-Zehnder optical modulator driver with high-voltage swing-driving capability. The modulator consists of a series-shunt inductor peaking predriver stage and a multicascode postdriver stage. The postdriver stage integrates the proposed inductive intrinsic parasitic feedback network, the interstage series inductor-peaking scheme, and the auxiliary source degeneration structure. The chip is fabricated in 0.13- μm mixed-signal 1P8M standard CMOS process with a die size of 900×800 μm2. The operation data rate of this design is measured up to 20-Gb/s with 3.7 VPP S.E. output amplitude swing, driving 50-Ω resistive load with input signal less than 250 mV. The measured rise/fall time of the output electrical eye diagram is less than 20 ps and the total power consumption is 0.9 W with 1.2/4.0 V dual supplies.

A load-balanced Birkhoff-von Neumann (LB-BvN) 4 × 4 switch fabric IC is proposed for feedback-based switch systems. This is fabricated in 0.13- μm CMOS technology and the chip area is 1.380 × 1.080 mm2. The overall data rate of the LB-BvN 4 × 4 switch fabric IC is up to 32 Gb/s (8 Gb/s/channel) with only 0.8 ns propagation delay. The LB-BvN switch is highly recommended for constructing the next-generation terabit switch. In a feedback-based switch system, the long propagation delay of the switch module reduces the system throughput significantly. In this paper, we present a scalable LB-BvN 4 × 4 switch fabric IC directly in the high-speed domain. By observing the deterministic switching pattern of the N×N LB-BvN switch, we present a low-complexity pattern generator that reduces the PG complexity from O(N3) to O(1). This technique reduces the propagation delay of the switch module from 30 to 0.8 ns, and also provides 80% area saving and 85% power saving compared to serializer-deserializer interfaces. The proposed LB-BvN 4 × 4 switch fabric IC is suitable for feedback-based switch systems to solve the throughput degradation problem.

In this paper, a low propagation delay, low power, and area-efficient 4×4 load-balanced switch circuit for feedback-based system is presented. In this periodic and deterministic switch, only two DFFs are used to implement a pattern generator which is a O(N3) hardware complexity in traditional matching algorithm based N×N switch. For packet reordering, a feedback path is established in series of symmetric patterns. As comparing with commercial switch systems, we implement a 4×4 switch IC directly in high speed domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. In CML output buffer, PMOS active load and active back-end termination are introduced. A stacked current source and symmetric topology in CML-DFF are adopted. From our results, this work efficiently deducted 28ns propagation delay, 80% area and 80% power introduced by the SERDES interface. The throughput rate is up to 32Gbps (8Gbps/Ch).

This paper presents a 10.0-11.5 Gb/s full-rate phase and frequency detector integrated with the clock recovery circuit (CRC) for application in optical receivers. A rotational phase and frequency detector (RPFD) without external reference clock is proposed to train the conventional bang-bang phase detector (BBPD) to capture the clock frequency. The proposed RPFD shows 1.5 GHz capture range and works in the high speed data rate of 10 Gb/s. Only one closed loop is used to track the internal clock. The acquisition time for the clock frequency to adjust from 11.5 to 10 GHz is 160 ns. The fabricated chip occupies 0.7 mm in 90 nm CMOS process with -108.8 dBc/Hz at 1-MHz offset and consumes 52 mW power with 1.0-V supply.

In this paper, a low propagation delay, low power, and area-efficient 4×4 load-balanced switch circuit for feedback-based system is presented. In this periodic and deterministic switch, only two DFFs are used to implement a pattern generator which is a O(N3) hardware complexity in traditional matching algorithm based N×N switch. For packet reordering, a feedback path is established in series of symmetric patterns. As comparing with commercial switch systems, we implement a 4×4 switch IC directly in high speed domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. In CML output buffer, PMOS active load and active back-end termination are introduced. A stacked current source and symmetric topology in CML-DFF are adopted. From our results, this work efficiently deducted 28ns propagation delay, 80% area and 80% power introduced by the SERDES interface. The throughput rate is up to 32Gbps (8Gbps/Ch).

A Combined Input and Crosspoint Queueing (CICQ) switch is a switch that has both buffers at the crosspoints of the switch fabric and buffers at the inputs. Inspired by the fixed frame based algorithm for an input-buffered switch and the smooth scheduling algorithm for a CICQ switch, in this paper we propose using a dynamic frame sizing algorithm for a CICQ switch. It is formally shown that such a CICQ switch indeed achieves 100% throughput for certain Poisson-like traffic models. This is done without using the framed Birkhoff-von Neumann decomposition needed. Moreover, such a CICQ switch only requires a two-cell buffer at each crosspoint when there is only unicast traffic. Unlike input-buffered switches, the dynamic frame sizing algorithm also achieves 100% throughput in the setting of multicast traffic. This is done at the cost of increasing the buffer size at each crosspoint.

In this paper, we present a 7 Gbps/Ch quad SerDes integrated with a 4times4 load-balanced switch fabric circuit for high speed networking applications. To achieve high-speed and low area, we propose an area-saving RF model device for the SerDes design. The area-saving RF model has almost the same speed and jitter performance with the RF model but only consumes one half of the area. In our hybrid design of the SerDes architecture, the area-saving RF model mixed with the baseband model can reduce 75% of area compared with the design using only the conventional RF model. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew for the quad SerDes to within 1 ps. The total area is 3 mm times 2.48 mm, including the switch fabric, the quad SerDes interface, and a LC-PLL. In our results, each input/output port of the 4x4 switch fabric can achieve 7 Gbps data rate, and the overall throughout is 28 Gbps.

For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES interface circuits for high speed networking applications. An N times N TDM switch could be constructed recursively from the TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8 times 8 TDM switch core with 8B10B CODECs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All implementation were based on the 0.18 mum CMOS technology. Our implementation showed a 20 Gbps switching capacity for the 8 times 8 TDM switch IC.

For the first time, a scalable load balanced Birkhoff-von Neumann TDM switch IC with SERDES interface circuits for high speed networking applications was implemented. AnyN×NBirkhoff-von Neumann TDM switch could be constructed recursively from the designed TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8×8 TDM switch core with 8B10B codecs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All the implementations were based on the 0.18 μm CMOS technology. Test results showed a 20 Gbps switching capacity for the 8×8 TDM switch IC.