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Erik A. Sandberg

dblp:31/5935 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
parallel programming models
0.011993
Formal Method for Scheduling, Routing and Communication Protocol · HPDC 1993
Parallel and multicore computing › parallel computation models
PRAM
0.011993
Formal Method for Scheduling, Routing and Communication Protocol · HPDC 1993
Parallel and multicore computing › parallel programming models
message passing
0.011993
Formal Method for Scheduling, Routing and Communication Protocol · HPDC 1993

Methods — techniques the papers use, named apart from their topics

psi calculus · 0.0
YearPublicationVenuePosition
1993 Formal Method for Scheduling, Routing and Communication Protocol
abstract
The PRAM model has been shown to be an optimal design for emulating both loose and tightly coupled multiprocessors for unit time operations. When virtual processors are required, multiplexing work to available processors is employed. This introduces a form of latency incurred by operating system overhead. Further complications arise when bandwidth creates bottlenecking of work units. G.E. Blelloch (1989) showed how to add parallel prefix operations (scans) to an extended PRAM model which uses unit step, not time operations. This paper shows how the Psi( psi ) calculus can be used to group work units, i.e. pipelining the work units, so that multiplexing is not required. The authors instead pipeline work units to processors and show how the number of processors need not be equivalent to the number of data components. Partitioning array data structures and pipelining groups of partitions to processors can minimize latency and bottlenecking on distributed message passing multiprocessing architectures.>
Lenore M. Restifo Mullin, Scott Thibault, Daria R. Dooling, Erik A. Sandberg
HPDC4