In this paper, we propose a novel approach that utilizes localized X-ray irradiation to amplify data-dependent leakage currents in CMOS-based cryptography circuits. Our proposed technique strategically targets specific regions in a circuit using X-rays, inducing variations in dynamic and static power consumption due to Total Ionizing Dose (TID) effects, which increases or even reveals hidden data leakage. In this work, we present several experimental campaigns highlighting the benefits of our approach to combinational and sequential logic. Our experiments show a significant increase in information leakage in the targeted regions, which improves the signal-to-noise ratio coefficient and thus makes recovering the processed bytes easier. We envision the possibility of using this technique on full cryptographic designs on both FPGA and ASICs.

Monitoring soil water content (SWC) using cosmic-ray neutron sensors is a method that relies on the faculty of hydrogen contained in soils to moderate neutrons. In this study, we evaluate the feasibility to use cosmic-ray neutron spectrometry to monitor SWC. A Bonner sphere spectrometer extended to high energies was operated since December 2022 on a highly monitored area, offering atmospheric and SWC time series. The first spectrometer installation was made within a building, and the second one outside. The temporal series were corrected from atmospheric pressure and compered with the soil moisture and atmospheric humidity variations. The results show that there is a strong inverse correlation between neutron fluxes measured outside the building and the SWC.

International audience

Modern technologies make hardware designs more and more sensitive to radiation particles and related faults. As a result, analysing the behavior of a system under radiation-induced faults has become an essential part of the system design process. Existing approaches either focus on analysing the radiation impact at the lower hardware design layers, without further propagating any radiation-induced fault to the system execution, or analyse system reliability at higher hardware or application layers, based on fault models that are agnostic of the fabrication technology and the radiation environment. Flodam combines the benefits of existing approaches by providing a novel cross-layer reliability analysis from the semiconductor layer up to the application layer, able to quantify the risks of faults under a given context, taking into account the environmental conditions, the physical hardware design and the application under study.

This work reports LFI experiments carried out on custom CMOS 65 nm digital test gates, aiming at tuning the parameters of a compact electrical model. Like in previous works, we observed a difference in behavior in the induced faults when using nanosecond and picosecond range laser pulse duration. However, our experimental results showed that the laser-sensitive areas were restricted to the PMOS transistors for ns laser pulses, contrary to what was previously stated in the literature. For ps pulse duration, these works outline the sensitivity of both the NMOS and PMOS of an SRAM cell following the theoretical model of LFI. These experiments help to calibrate the parameters of a compact electrical model, allowing the simulation of LFI attacks (using SPICE-like CAD tools). This compact model is built upon previous works, with simplifications to facilitate its use. Once tuned, simulations using the proposed compact model exhibit a good correlation with the experimental results.

Studies on laser induced IR-drop are recent and still not much covered. Since laser-induced IR-drop can amplify the well-known effects of induced photoelectric currents in ICs, this work aims to present important characteristics of such effect. Understanding the characteristics and effects of laser induced IR-drop in ICs allows the elaboration of more accurate simulation models, and consequently helps in the design of countermeasures that mitigate the effects of laser illumination. Simulations and experiments were performed in order to understand the relationship of the laser pulse width and the decoupling capacitance of the power supply network with the induced IR-drop. The results showed that the maximum variation of the supply voltage depends on the laser pulse duration, and on other circuit characteristics, such as RLC parameters of the supply network. It was possible to observe by simulations and experiments that, for the proposed circuit, the maximum variation of the supply voltage occurred for a laser pulse greater than or equal to 1 μs. Regarding the decoupling capacitance variation, the results showed that for a decoupling capacitor up to 100 pF, the IR-drop becomes even more relevant with a variation up to 97% of VDD.

The yield optimization and radiation hardness are relevant reliability requirements as chip manufacturing advances more in-depth into the nanometer regime. One way to obtain improvements in these issues is by applying techniques to mitigate the effects of process variability and radiation-induced soft errors in the circuits. This work reports the use of three circuit-level approaches in FinFET designs as well as point out the pros and cons of adopting it.

Lasers have become one of the most efficient means to attack secure integrated systems. Actual faults or errors induced in the system depend on many parameters, including the circuit technology and the laser characteristics. Understanding the physical effects is mandatory to correctly evaluate during the design flow the potential consequences of a laser-based attack and implement efficient counter-measures. This paper presents results obtained within the LIESSE project, aiming at defining a comprehensive approach for designers. Outcomes include the definition of fault/error models at several levels of abstraction, specific CAD tools using these models and new counter-measures well-suited to thwart laser-based attacks. Actual measures on components manufactured in the new 28 nm FDSOI technology are also presented.

The goal of this work is to confront SER predictions done with MUSCA SEP3 to measures performed at high altitude (in commercial planes) by means a generic and flexible experimental testboard developed by TIMA. In this case the testboard was a memory architecture of 1 Gigabit made from SRAMs issued from two successive generations, 130 nm and 90 nm, respectively named models 1 and 2 in the following.

This paper presents a methodology for analyzing the behavior of nanometer technologies regarding "multiple event transients" (MET) caused by nuclear reaction induced by atmospheric neutrons. For the first time, currents collected by several sensitive areas of an ASIC cell resulting from a nuclear reaction are addressed by simulation. Libraries of several thousand types of currents are obtained for neutron energy range between 1 and 200 MeV. Group of currents are simultaneously injected at SPICE level and their effects are monitored on the cell output. Following an amplitude criterion, output transient duration and associated occurrence probability are recorded. A 130 nm NAND gate from ATMEL Corporation is first used to illustrate the methodology and a comparison between single event transients and multiple event transients effects is presented Finally, results regarding five different combinational cells in the ATMEL 130 nm library are presented and discussed.

This paper presents a new Monte-Carlo methodology to investigate the transient effect occurrence in complementary metal oxide semiconductor (CMOS) logic circuits: TMC DASIE (transient Monte-Carlo detailed analysis of secondary ion effects). The production and effects of single-event transients inside CMOS combinational logic gates are examined. First results and perspectives are presented

DASIE (the detailed analysis of secondary ion effect) is the name of a code family dedicated to the SEE rate prediction. This paper presents a review of DASIE code family and its contributions to SEU (single event upset) and MBU (multiple bit upset) understanding.