We describe architectures for audio classification front ends on a reconfigurable analog platform. Real-time implementation of audio processing algorithms involving discrete-time signals tend to be power-intensive. We present an alternate continuous-time system implementation of a noise-suppression algorithm on our reconfigurable chip, while detailing the design considerations. We also describe a framework that enables future implementations of other speech processing algorithms, classifier front ends, and hearing aids.

Power management in loudspeakers is used to extend the battery life of portable electronics and to prevent thermal damage to the speakers. Traditionally, speaker power management has been implemented as an adaptive gain control, which limits the power applied to the loudspeaker uniformly. In this pa per, we present a perception-based algorithm that suppresses inaudible contents from the audio before sending it to the amplifier and loudspeaker. The power reduction algorithm attenuates the signal energy in the digital domain. Subjective test results show that the energy reduction is largely unnoticeable in small loudspeakers.

The design of analog classifiers constitutes a trade- off between performance and complexity, and designers have historically adopted more complex architectures to lower the error rate of a classification task. An alternative design paradigm is presented in this paper: We design the front-end of a sound classification system with simple "base" classifiers. We then enhance the overall performance with the aid of the AdaBoost algorithm, which selects the most appropriate "base" classifiers and combines them with different weights. We describe the general architecture and the algorithm to select features and present a design example with simulation results in a TSMC- compatible 0.35-μm technology.

This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

This paper discusses the application of a computational image sensor, capable of performing separable 2-D transforms on images in the analog domain, to compressive sensing. Instead of sensing and transmitting raw pixel data, this image sensor first projects the image onto a separable 2-D basis set. The inner products computed in these projections are computed in the analog domain using a computational focal-plane and a computational analog vector-matrix multiplier. Since this operation is performed in the analog domain, components such as the analog-to-digital converters can be taxed less when a only subset of correlations are performed. Compressed sensing theory prescribes the use of a pseudo-random, incomplete basis set, allowing for sampling at less than the Nyquist rate. This can reduce power consumption or increase frame rate.