As AI and its applications evolve, efficient hardware is required to run the novel algorithms. Compute platforms with a high degree of parallelism, such as matrix-vector multipliers, meet the need to process large homogeneous loads of operations. However, most of the matrix-vector multiplications required by the AI algorithms are larger than what the actual hardware supports. The operations must therefore be tiled into blocks that fit on the given hardware. Finally, the partial sums generated by the hardware for each tile must be accumulated or concatenated into the complete result. Especially with mixed-signal compute-in-memory architectures, this can lead to quantization on two levels. First, an ADC quantizes the partial sums generated for each tile. Then, the algorithm performs another quantization of the final result to limit bitwidth and resource consumption in adjacent computations. While quantizing only the partial sums or only the final results has been studied extensively, the combination of the two has yet to be investigated. This work introduces a simulator to understand the effects of quantization caused by multiple quantization steps on different levels. It is based on a generic, stochastic representation of value probabilities using histograms. Common operations such as scaling, rounding, and accumulation are implemented in this representation, allowing the effect of quantization to be studied in a matrix-vector-multiplier application. It is shown, that the selection of tilesize, ADC bitwidth and clipping technique form a complex trade-off, which can be solved using PSumSim. PSumSim is available under https://github.com/Joschua-Conrad/PSumSim.

The theory of incremental Delta-Sigma (I-DS) converters relies on memoryless operation between consecutive Nyquist samples. This is achieved by resetting the analog loop-filter and digital reconstruction filter every Nyquist period. It is shown that the use of reconstruction filters with negligible first-sample weights opens the possibility of removing the periodic reset from the analog loop filter of incremental Delta-Sigma modulator (I-DSM) while maintaining memoryless operation. The periodic reset can further be removed from reconstruction filters whose impulse response is inherently finite. Combining the two features enables free-running Delta-Sigma (DS) converters to be used in time-domain multiplexing applications and without inter-channel interference.

Continuous-time (CT) Delta-Sigma (DS) ADCs are a popular choice for high resolution, medium bandwidth applications. A critical challenge is the excess-loop-delay (ELD) in the feedback path of the modulator, which causes performance degradation and instability. For free-running Delta-Sigma modulators (DSMs), performance can be fully recovered by adjusting the loop filter to restore the original noise transfer function (NTF) without ELD. For CT incremental Delta-Sigma (I-DS) ADCs, this has not been specifically investigated, but it is worth noting that the process of ELD compensation is slightly different. In this paper, we investigate the effect of ELD on I-DS ADCs and show that the performance cannot be fully recovered by NTF engineering as in the free-running case, but requires signal transfer function (STF) engineering as well. We also present solutions on how to engineer the STF and how to fully recover the performance even in the presence of ELD in CT I-DS ADCs.

The maximum stable amplitude (MSA) is an important characteristic of a Delta-Sigma modulator (DSM) for high resolution and power efficiency. In free-running DSMs it is known that the MSA usually corresponds to a similar value as the amplitude with the maximum signal-to-quantization-noise ratio (SQNR) and that it depends on several factors including: loopfilter architecture, loopfilter scaling and aggressiveness, internal quantizer bit-width, signal transfer function (STF) and input frequency. Commonly, incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are derived from free-running prototypes enhanced by a periodic reset, and the assumption is that the underlying characteristics remain the same. In contrast, we elaborate in this work that the MSA of I-DS ADCs doesn’t correspond to the amplitude with the maximum SQNR anymore and that this amplitude is not exclusively determined by the DSM, but also depends on the chosen reconstruction filter. Furthermore, the reasons for this interdependency of the reconstruction filter and the amplitude with maximum SQNR are highlighted and solutions to solve this problem are presented.

Element mismatch error shaping had been thoroughly studied in free-running Delta-Sigma (DS) ADCs, which enabled using multi-bit quantizer in the loopfilter while shaping the non-linearity errors of the feedback DAC unit element mismatch. A popular shaping technique in free-running DS ADCs is the simple rotational data-weighted averaging (DWA), which was shown to be ineffective in state of the art (SoA) higher order incremental Delta-Sigma (I-DS) ADCs. Hence, prior SoA proposed smart shaping techniques tailored for I-DS ADCs, though adding significant area and power complexity compared to DWA. In this work it is shown that by applying periodic reset to the DWA’s rotation index renders it very feasible and effective for DAC mismatch shaping even in higher order I-DS ADCs without the need of changed algorithms.

The offset cancellation in incremental Delta-Sigma (IDS) ADCs has to be treated differently compared to the cancellation in their freerunning counterparts. In the state of the art (SoA), there exists a lack of theory about this topic. Therefore, in this paper offset propagation and cancellation in I-DS ADCs is analysed. Thereby the idea of fractal sequences to cancel the offset is revised and extended to a more general description to cancel the offset at the output of the I-DS ADC. The derived theory is further explained and backed up by simulations for an exemplary modulator architecture. The intention is to give a deeper understanding on the offset propagation and cancellation in I-DS ADCs and close this gap in the SoA.

This paper introduces an Artificial Neural Network (ANN) to predict the stability of Delta-Sigma modulators (DSMs) and, furthermore, shows its beneficial employment in a genetic optimization algorithm. Since a DSM is a non-linear system, its stability often can’t be predicted by simple algebra. Therefore, a new approach predicting the stability of DSMs using an ANN is presented in this work. It is shown how the data generation and training of such a network can be done. Furthermore, the derivation of high-level coefficients for DSMs is a tedious task, which is often solved by time consuming simulations. The application of the derived ANN in a genetic algorithm to find these high-level coefficients leads to the significant time savings of close to 50%.

In this paper, the linear-exponential incremental Delta-Sigma (I-DS) ADC is analyzed as a dynamic reconfiguration technique. The influence of the parameters of the exponential phase on the performance of the ADC will be analysed and further investigated under the presence of coefficient mismatch. Furthermore, higher order linear-exponential I-DS ADCs will be introduced and the analysis is extended from first to higher order modulators, giving valuable insights and showing the benefits and drawbacks of higher order linear-exponential I-DS ADCs compared to first order ones. The intention is to give an insight and understanding of the performance improvements, limiting factors and trade-offs achieved by the exponential phase.

In this paper, analysis of linear time-variant systems is applied to incremental Delta-Sigma (I-DS) ADCs with periodic architectural reconfiguration in the frequency domain. The analysis will then be applied to the example of linear-exponential I-DS ADCs as a state-of-the-art dynamic reconfiguration technique. It is shown how a matched reconstruction filter of the reconfigured linear-exponential incremental Delta-Sigma modulator (I-DSM) can be mathematically derived. Using the calculated overall transfer functions of the linear-exponential I-DS ADC, accurate performance predictions can be given. The proposed method allows the accurate prediction of performances and gives insight and understanding of the performance improvements and trade-offs achieved by reconfiguration techniques in I-DS ADCs in general and the exponential phase in particular.