This paper proposes a Vref-compensated memristor-assisted CDAC background calibration scheme for Nyquist SAR ADCs. The proposed CDAC is implemented in a 12-bit 5 MS/s asynchronous SAR ADC featuring a Vcm-based switching scheme and designed using a standard 65 nm CMOS process. Capacitor mismatches are detected by introducing a redundant bit, which evaluates the sign of the mismatch error. This error is then calibrated through a feedback loop using voltage dividers with four integrated memristors. These programmable voltage dividers generate a compensating voltage that is added to or subtracted from the ADC reference voltage (Vref) based on the sign of the mismatch error. Consequently, the adjusted Vrefcompensates the CDAC output level to reduce non-linearity induced by capacitor mismatches. Simulation results validate the feasibility of optimizing non-linearity in moderate/high-resolution SAR ADCs (12-bit in this study) caused by capacitor mismatches, improving the signal-to-noise-and-distortion ratio (SNDR) from 41.85 dB to 65.98 dB with memristor-assisted analog circuits. The proposed SAR ADC occupies 0.0153 mm2area according to the layout floorplan, making it a promising candidate for miniature/large-scale sensor interface application.

CMOS scaling involves more than just reducing the effective channel length—it has become increasingly complex. Aligning the circuit design ecosystem with semiconductor technology is now more critical than ever, giving rise to the Design-Technology Co-Optimization (DTCO) concept and further extending Moore’s Law. This live demonstration presents our previously published N2 nanosheet Pathfinding PDK (P-PDK) which provides insight into cutting-edge CMOS technology under the framework of DTCO. This session will cover the motivation behind developing this cutting-edge PDK, the basic flow of using the P-PDK, and the prospects of the P-PDK.

High-resolution ADCs require low noise and low distortion while consuming minimal power. This paper presents a power-efficient, calibration-free, 2nd-order noise-shaping (NS) SAR ADC. Mismatch error shaping (MES) is employed to reduce distortion from capacitive DAC mismatches. The resulting input range loss is compensated for by an additional digital prediction (DP) method. To mitigate the high power consumption of the multi-input dynamic comparator, this work proposes a coarse-fine comparison (CFC) scheme, enabling the ADC to switch between SAR and NS-SAR modes. This approach reduces the power consumption of the comparator while maintaining NS functionality. Furthermore, to eliminate the need for an external high-speed clock to control SAR logic and NS operation, this work utilizes a fully asynchronous logic driven solely by a sample-and-hold clock. Implemented in standard 130-nm CMOS technology, this prototype ADC achieves a measured 81.54-dB SNDR (13.25-bit ENOB) in a 100-kHz bandwidth with an oversampling ratio (OSR) of 25.

The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor's response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into account. This paper proposes an optimized data-driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further introduce a new concept “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

The memristor, because of its controllability over a wide dynamic range of resistance, has emerged as a promising device for data storage and analog computation. A major challenge is the accurate measurement of memristance over a wide dynamic range. In this paper, a novel read-out circuit with feedback adjustment is proposed to measure and digitise input current in the range between 20nA and 2mA. The magnitude of the input currents is estimated by a 5-stage logarithmic current-to-voltage amplifier which scales a linear analog-to-digital converter. This way the least significant bit tracks the absolute input magnitude. This circuit is applicable to reading single memristor conductance, and is also preferable in analog computing where read-out accuracy is particularly critical. The circuits have been realized in Bipolar-CMOS-DMOS (BCD) Gen2 technology.