Tiered memory systems typically place pages based on access frequency (hotness), yet frequency alone fails to capture the true performance impact. We present PACT, an online, page-granular tiered memory design that elevates performance criticality to a first-class design principle. At its core is Per-page Access Criticality (PAC), a fine-grained metric that quantifies each page's contribution to application performance rather than merely counting accesses. PACT profiles PAC online using a lightweight analytical model that uniquely decomposes per-tier memory-level parallelism via hardware queue occupancy counters, enabling direct CPU stall attribution to individual pages. To handle highly skewed PAC distributions, PACT employs PAC-centric migration policies: eager demotion and adaptive promotion, to dynamically place performance-critical pages in DRAM. Across 13 workloads, PACT achieves up to 61% performance improvement over the best of 7 state-of-the-art tiering designs with up to 50× fewer migrations.

Compute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-μs CXL latencies (140-410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (SPA) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL.

We propose RETINA-a unified key-value store (KVS) with computational pipeline framework natively designed for computational storage. Retina proposes a cross-layered architecture to leverage CPU as the control plane and near-storage FPGA as the compute & data plane which is key to reducing the data movement and achieving high-performance. Retina Kvs includes near-storage Arbiter implemented on the FPGA which is capable of scheduling tasks, manage memory, and establish communication between the host CPU and the near-storage FPGA. Retina enables applications to compose and offload compute to the storage during the run time with a familiar set of KVS-style APIs. We evaluate Retina by integrating it to TensorFlow machine learning framework and training the ResNet50 DL model by offloading the entire image preprocessing steps to the near-storage FPGA. Overall, Retina performs up to 75% faster and saves up to 65% CPU time against CPU-only systems.