Navigation instruction generation (NIG), which provides interactive feedback and guidance to humans along a trajectory, is vital for developing embodied agents capable of human-machine communication and collaboration through natural language. Early data-driven methods directly map sequences of past observations to trajectory descriptions on limited datasets, lacking the necessary spatial understanding in complex 3D environments. While recent approaches leverage Large Language Models (LLMs) to improve NIG, they often overlook the global spatial context in navigation, such as the inherent space discretization in maps. Instead of straightforwardly feeding textual descriptions of the map into LLMs, we propose a scene map-based prompt tuning framework for NIG, MAPInstructor, which incorporates map context for parameter-efficient updating of LLMs. MAPInstructor comprises three key components: (i) scene representation encoding, where egocentric observations are projected into 3D voxels for fine-grained scene understanding; (ii) map prompt tuning, which integrates a topological map representation of the entire trajectory into an LLM-based decoder; and (iii) landmark uncertainty assessment, which mitigates hallucinations in landmark predictions, thereby enhancing the reliability and coherence of instruction generation. Extensive experiments on three navigation datasets (i.e., R2R, REVERIE, RxR) confirm the generalization and effectiveness of our algorithm.

This brief utilizes the logarithmic number system (LNS) to realize the half-precision division (DIV), square root (SR), and inverse SR (ISR) that are widely used in both the error resilience application and high-performance computing. With the aid of similarities of logarithmic and antilogarithmic functions, the adder tree and multiplexer in the shift-and-add architecture can be shared by the Log and Antilog converter. Moreover, a novel architecture for DIV and SR based on the fused converter is proposed. Compared to the existing works, this new architecture not only achieves a good tradeoff between precision level and hardware efficiency, but also can support more operations (e.g., exponential function, multiplication) with negligible hardware resources. In addition, the proposed architecture can be easily pipelined to further increase the throughput. Furthermore, for some formulas requiring multiple basic operations (e.g., ISR), the advantage of the LNS is more significant.