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J. Nohava

dblp:314/5192 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › optical interconnection networks
free-space optical interconnects
0.012000
Smart-pixel array technology for free-space optical interconnects · Proc. IEEE 2000
Interconnection networks and networks-on-chip
optical interconnection networks
0.012000
Smart-pixel array technology for free-space optical interconnects · Proc. IEEE 2000
Integrated circuit design
optoelectronic integrated circuits
0.012000
Smart-pixel array technology for free-space optical interconnects · Proc. IEEE 2000
YearPublicationVenuePosition
2000 Smart-pixel array technology for free-space optical interconnects
abstract
This paper describes a smart-pixel array technology that is being developed at Honeywell for use in chip-to-chip optical interconnections based on free-space optics. The technology combines large-scale, two-dimensional arrays of optoelectronic and microoptical elements with VLSI electronics to enable high-density, high-speed interchip input/output capability in the optical domain. We have demonstrated prototype modules with 16/spl times/16 and 32/spl times/32 emitter and interleaved detector arrays.
E. M. Strzelecka, J. Nohava, Mary K. Hibbs-Brenner, Elias Towe
Proc. IEEE3