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Maysam Rahmanpour

dblp:314/6469 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 54% Storage systems · 46%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
non-volatile memory
0.612022
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers · IEEE Trans. Parallel Distributed Syst. 2022
Storage systems › storage reliability › durability
retention failure
0.612022
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers · IEEE Trans. Parallel Distributed Syst. 2022
Memory systems › non-volatile memory › magnetic random access memory
STT-MRAM
0.612022
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers · IEEE Trans. Parallel Distributed Syst. 2022
Memory systems
DRAM
0.212022
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers · IEEE Trans. Parallel Distributed Syst. 2022

Methods — techniques the papers use, named apart from their topics

distant refreshing · 0.6
YearPublicationVenuePosition
2022 CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers
abstract
Performance and reliability are two prominent factors in the design of data storage systems. To achieve higher performance, recently storage system designers use$Dynamic$$RAM$(DRAM)-based buffers. The volatility of DRAM brings up the possibility of data loss and data inconsistency. Thus, a part of the main storage is conventionally used as the journal area to be able of recovering unflushed data pages in the case of power failure. Moreover, periodically flushing buffered data pages to the main storage is a common mechanism to preserve a high level of reliability. This scheme, however, leads to a considerable increase in storage write traffic, which adversely affects the performance. To address this shortcoming, recent studies offer a small$Non-Volatile$$Memory$(NVM) as the$Persistent$$Journal$$Area$(PJA) along with DRAM as an efficient approach to overcome DRAM vulnerability against power failure while effectively reducing storage write traffic. This approach, named$NVM-Backed$$Buffer$(NVB-Buffer), features from advantages of NVMs and addresses DRAM shortcomings. In this article, we employ the most promising technologies for PJA among the emerging technologies, which is$Spin-Transfer$$Torque$$Magnetic$$Random$$Access$$Memory$(STT-MRAM) to meet the requirements of efficient PJA by providing high endurance, non-volatility, and DRAM-like latency. Despite these advantages, STT-MRAM faces major reliability challenges, i.e.,Retention Failure,Read Disturbance, andWrite Failure, which havenotbeen addressed in previously suggested NVB-Buffers. In this article, we first demonstrate that the retention failure is the dominant source of errors in NVB-Buffers as it suffers from long and unpredictable page idle intervals (i.e., the time interval between two consecutive accesses to a PJA page). Then, we propose a novel NVB-Buffer management scheme, named,$\underline{Co}ld$$\underline{P}age$$\underline{A}wakening$(CoPA), which predictably reduces the idle time of PJA pages. To this aim, CoPA employs$Distant$$Refreshing$to periodically overwrite the vulnerable PJA page contents by opportunistically using their replica in DRAM-based buffer. We compare CoPA with the state-of-the-art schemes over several well-known storage workloads based on physical journaling. Our evaluations show that CoPA significantly reduces the maximum page idle time, which leads to three orders of magnitude lower failure rate with negligible performance degradation (1.1%) and memory overhead (1.2%).
Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi 0001
IEEE Trans. Parallel Distributed Syst.3