Modern System-on-Chip functionalities include significant software interacting closely with low-level hardware to realize system functionalities. This software is developed concurrently with the hardware and must be validated before the hardware is fabricated. Current industrial practice depends on the creation of virtual prototyping environments to enable the validation of such software. However, creating such prototypes is complicated, manual, and error-prone. In this paper, we propose a novel infrastructure, for automatically generating virtual prototyping environments. includes an architecture and CAD flow to integrate different design blocks available in different abstraction levels to create a coherent, uniform view of SoC functionality suitable for early software validation. We show several case studies illustrating the applicability of .

We present an infrastructure, FirVer, for systematic validation of firmware binaries. FirVer makes unique use of virtual prototyping and unit testing interfaces for effective comprehension of hardware-firmware. We used FirVer on several library functions of TianoCore, a full-featured UEFI-compatible boot firmware developed by Intel Corporation. FirVer achieved more than 90% in line and function coverages, and between 60% and 80% branch coverage. FirVer also enabled exploration of corner cases that exposed segmentation faults in many constituent functions.