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Rafael Fontella Katopodis

dblp:314/9953 · DBLP profile ↗
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5ranked-venue papers
2as first author
5since 2021 · last 2023
0000-0002-7902-3103ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Artificial intelligence and machine learning · 2 · 2 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 61% Reconfigurable computing and FPGAs · 30% Energy-efficient computing · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference accelerator
edge inference accelerator
0.712023
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks · ACM Trans. Archit. Code Optim. 2023
Reconfigurable computing and FPGAs
FPGA accelerator
0.712023
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks · ACM Trans. Archit. Code Optim. 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.712023
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks · ACM Trans. Archit. Code Optim. 2023

Methods — techniques the papers use, named apart from their topics

table lookup · 0.7binary neural network training · 0.7
YearPublicationVenuePosition
2023 ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks
abstract
‘‘Extreme edge” 1 devices, such as smart sensors, are a uniquely challenging environment for the deployment of machine learning. The tiny energy budgets of these devices lie beyond what is feasible for conventional deep neural networks, particularly in high-throughput scenarios, requiring us to rethink how we approach edge inference. In this work, we propose ULEEN, a model and FPGA-based accelerator architecture based on weightless neural networks (WNNs). WNNs eliminate energy-intensive arithmetic operations, instead using table lookups to perform computation, which makes them theoretically well-suited for edge inference. However, WNNs have historically suffered from poor accuracy and excessive memory usage. ULEEN incorporates algorithmic improvements and a novel training strategy inspired by binary neural networks (BNNs) to make significant strides in addressing these issues. We compare ULEEN against BNNs in software and hardware using the four MLPerf Tiny datasets and MNIST. Our FPGA implementations of ULEEN accomplish classification at 4.0–14.3 million inferences per second, improving area-normalized throughput by an average of 3.6× and steady-state energy efficiency by an average of 7.1× compared to the FPGA-based Xilinx FINN BNN inference platform. While ULEEN is not a universally applicable machine learning model, we demonstrate that it can be an excellent choice for certain applications in energy- and latency-critical edge environments.
Zachary Susskind, Aman Arora 0001, Igor D. S. Miranda, Alan T. L. Bacellar, Luis A. Q. Villon, Rafael Fontella Katopodis, Leandro Santiago de Araújo, Diego Leonel Cadette Dutra, Priscila M. V. Lima, Felipe M. G. França, Maurício Breternitz, Lizy Kurian John
ACM Trans. Archit. Code Optim.6
2022 Weightless Neural Networks for Efficient Edge Inference
abstract
Weightless neural networks (WNNs) are a class of machine learning model which use table lookups to perform inference, rather than the multiply-accumulate operations typical of deep neural networks (DNNs). Individual weightless neurons are capable of learning non-linear functions of their inputs, a theoretical advantage over the linear neurons in DNNs, yet state-of-the-art WNN architectures still lag behind DNNs in accuracy on common classification tasks. Additionally, many existing WNN architectures suffer from high memory requirements, hindering implementation. In this paper, we propose a novel WNN architecture, BTHOWeN, with key algorithmic and architectural improvements over prior work, namely counting Bloom filters, hardware-friendly hashing, and Gaussian-based nonlinear thermometer encodings. These enhancements improve model accuracy while reducing size and energy per inference. BTHOWeN targets the large and growing edge computing sector by providing superior latency and energy efficiency to both prior WNNs and comparable quantized DNNs. Compared to state-of-the-art WNNs across nine classification datasets, BTHOWeN on average reduces error by more than 40% and model size by more than 50%. We demonstrate the viability of a hardware implementation of BTHOWeN by presenting an FPGA-based inference accelerator, and compare its latency and resource usage against similarly accurate quantized DNN inference accelerators, including multi-layer perceptron (MLP) and convolutional models. The proposed BTHOWeN models consume almost 80% less energy than the MLP models, with nearly 85% reduction in latency. In our quest for efficient ML on the edge, WNNs are clearly deserving of additional attention.
Zachary Susskind, Aman Arora 0001, Igor D. S. Miranda, Luis A. Q. Villon, Rafael Fontella Katopodis, Leandro Santiago de Araújo, Diego Leonel Cadette Dutra, Priscila M. V. Lima, Felipe M. G. França, Maurício Breternitz, Lizy Kurian John
PACT5
2022 LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
abstract
Weightless neural networks (WNNs) are an alternative pattern recognition technique where RAM nodes function as neurons. As both training and inference require mostly table lookups, few additions, and no multiplications, WNNs are suitable for high-performance and low-power embedded applications. This work introduces a novel approach to implement WiSARD, the leading WNN state-of-the-art architecture, completely eliminating memories and arithmetic circuits and utilizing only logic functions. The approach creates compressed minimized implementations by converting trained WNN nodes from lookup tables to logic functions. The proposed LogicWiSARD is implemented in FPGA and ASIC technologies to illustrate its suitability for edge inference. Experimental results show more than 80% reduction in energy consumption when the proposed LogicWiSARD model is compared with a multilayer perceptron network (MLP) of equivalent accuracy. Compared to previous work on FPGA implementations for WNNs, convolutional neural networks, and binary neural networks, the energy savings of LogicWiSARD range between 32.2% and 99.6%.
Igor D. S. Miranda, Aman Arora 0001, Zachary Susskind, Luis A. Q. Villon, Rafael Fontella Katopodis, Diego Leonel Cadette Dutra, Leandro Santiago de Araújo, Priscila M. V. Lima, Felipe M. G. França, Lizy Kurian John, Maurício Breternitz
ASAP5
2022 Functional gradient descent for n-tuple regression
Rafael Fontella Katopodis, Priscila M. V. Lima, Felipe M. G. França
Neurocomputing1
2021 Functional Gradient Descent for n-Tuple Regression
abstract
n-tuple neural networks have been in the past applied to a wide range of learning domains.However, for the particular area of regression, existing systems have displayed two shortcomings: little flexibility in the objective function being optimized and an inability to handle nonstationarity in an online learning setting.A novel n-tuple system is proposed to address these issues.The new architecture leverages the idea of functional gradient descent, drawing inspiration from its use in kernel methods.Furthermore, its capabilities are showcased in two reinforcement learning tasks, which involves both nonstationary online learning and task-specific objective functions.
Rafael Fontella Katopodis, Priscila M. V. Lima, Felipe M. G. França
ESANN1