High performance microprocessors employed within autonomous systems usually adopt Fully Integrated Voltage Regulators (FIVRs) to enable the central power management unit to control individually the voltage of different microprocessor power domains, thus enabling a significant improvement of performance-per-Watt. However, since FIVRs are mainly implemented on the microprocessor die, they suffer from reliability problems due to the scaling of microelectronic technology. In particular, faults and aging may affect FIVRs during their in-field operation, possibly compromising the microprocessor correct operation in the field, with possible catastrophic effects if the microprocessor is executing safety critical functionalities of autonomous systems. In this paper, first we will analyze the effects of most likely faults and Bias Temperature Instability (BTI) aging mechanisms possibly affecting the FIVR during its operation in the field. We will show that almost 60% of FIVR faults may result in an incorrect output voltage, possibly compromising the microprocessor correct operation. Moreover, we will show that, due to BTI, the time it will take for the FIVR to change its output voltage in response to changes of its input reference voltage may exceed the maximum tolerable time guaranteeing the microprocessor correct operation. Based on these achieved results, we will then propose a monitor to enable the FIVR on-line test. In particular, upon the generation of an incorrect FIVR output voltage, or in case of a degraded FIVR response time to changes of the reference voltage (due to the occurrence of the considered faults or BTI), the monitor generates an output error message, that can then be adopted to activate proper recovery actions to guarantee the FIVR reliable operation, thus avoiding that faults and BTI possibly affecting FIVRs during their operation in the field can compromise the microprocessor correct operation, with possible dramatic consequences if the microprocessor is executing safety-critical functionalities.

Error Correcting Codes (ECCs) are frequently adopted to guarantee the correct operation in the field of caches of high performance microprocessors. They require the addition of proper encoding/decoding blocks (referred to as checkers) to the cache array. The occurrence of faults affecting such checkers has been typically neglected so far, due to their limited area compared to the cache array. This may be no longer acceptable, due to the increasing likelihood of faults possibly affecting microprocessors implemented by deeply scaled technologies, and due to the increasing requirements in terms of reliability of several applications (e.g., data centers, autonomous vehicles, unmanned robots, etc.). Based on these considerations, in this paper we analyze the effects of bridging faults possibly affecting the ECCs’ checkers, for two frequently adopted kinds of ECCs. We will show that the $68 \%$ (or the $61 \%$) of BFs possibly affecting the considered ECCs’ checkers are critical, since they may either inhibit the ECC correction ability of incorrect words read from the cache, or introduce errors in otherwise correct words read from the cache, with consequent risks for silent data corruption and microprocessor reliability. The remaining $\mathbf{3 2 \%}$ (or $39 \%$) of BFs may remain latent and accumulate with following faults or aging conditions affecting the cache, with consequent future risks for silent data corruption and microprocessor reliability. We then introduce a possible scheme to detect on line the occurrence of critical BFs that, compared to an alternate solution presented in the literature, features significantly lower impact on the ECC checker delay and area.