The coexistence of heterogeneous sub-networks in 6G poses new security and trust concerns and thus calls for a perimeterless-security model. Blockchain radio access network (B-RAN) provides a trust-building approach via repeated interactions rather than relying on pre-established trust or central authentication. Such a trust-building process naturally supports dynamic trusted services across various service providers (SP) without the need for perimeter-based authentications; however, it remains vulnerable to environmental and system unreliability such as wireless channel uncertainty. In this study, we investigate channel unreliability in the trust-building framework based on repeated interactions for secure wireless services. We derive specific requirements for achieving cooperation between SPs and clients via a repeated game model and illustrate the implications of channel unreliability on sustaining trusted wireless services. We consider the framework design and optimization to guarantee SP-client cooperation, given the worst channel condition and/or the least cooperation willingness. Furthermore, we explore the maximum cooperation area to enhance service resilience and reveal the trade-off relationship between transmission efficiency, security integrity, and cooperative margin. Finally, we present simulations to demonstrate the system performance over fading channels and verify our results.

This article proposes a phase-locked loop (PLL) based on the direct digital synthesis (DDS)/digital-to-analog converter (DAC) and the double-edge zero-crossing sampling phase detector (DS-PD) for frequency-modulated continuous-wave (FMCW) radar. Its DS-PD and frequency divider are combined to achieve refined time resolution while effectively expanding the phase lock range, thus eliminating the frequency-locked loop (FLL). The DDS/DAC is used to generate FMCW signals while achieving fast frequency hopping. A differential eight switching current unit is proposed to implement an ultrahigh-speed time-interleaved DAC. The 8.55–17.11-GHz PLL prototype, fabricated in 65-nm CMOS, consumes 10.11 mW with 0.29-mm2active area, while the DDS/DAC consumes 12.0 mW with a 0.16-mm2active area. The measured in-band phase noise (PN) at a 17.11-GHz output is −120.2 dBc/Hz at a 1-MHz offset with a root-mean-square (rms) jitter of 51.7 fs. The reference spur is$3.6~\mu \text{s}$) and precise (105-kHzrms frequency error) triangular chirps for FMCW radar applications.