VLDB 2026 Research / reviewers in the wild / expert
Yunuo Cen
dblp:317/0314
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2025
0009-0002-4679-9340ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 67% Algorithms and data structures · 33% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Algorithms and data structures › fourier transform
fast fourier transform |
0.9 | 1 | 2025 | Massively Parallel Continuous Local Search for Hybrid SAT Solving on GPUs · AAAI 2025 |
Automated reasoning and model checking › satisfiability › SAT solving
parallel SAT solving |
0.9 | 1 | 2025 | Massively Parallel Continuous Local Search for Hybrid SAT Solving on GPUs · AAAI 2025 |
Automated reasoning and model checking
satisfiability |
0.9 | 1 | 2025 | Massively Parallel Continuous Local Search for Hybrid SAT Solving on GPUs · AAAI 2025 |
GPUs and heterogeneous computing
GPU computing |
0.3 | 1 | 2025 | Massively Parallel Continuous Local Search for Hybrid SAT Solving on GPUs · AAAI 2025 |
Methods — techniques the papers use, named apart from their topics
parallel convolution · 1.7gradient-driven search · 1.7fast fourier transform · 1.7continuous local search · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Massively Parallel Continuous Local Search for Hybrid SAT Solving on GPUsabstractAlthough state-of-the-art (SOTA) SAT solvers based on conflict-driven clause learning (CDCL) have achieved remarkable engineering success, their sequential nature limits the parallelism that may be extracted for acceleration on platforms such as the graphics processing unit (GPU). In this work, we propose FastFourierSAT, a highly parallel hybrid SAT solver based on gradient-driven continuous local search (CLS). This is achieved by a parallel algorithm inspired by the fast Fourier transform (FFT)-based convolution for computing the elementary symmetric polynomials (ESPs), which is the major computational task in previous CLS methods. The complexity of our algorithm matches the best previous result. Furthermore, the substantial parallelism inherent in our algorithm can leverage the GPU for acceleration, demonstrating significant improvement over the previous CLS approaches. FastFourierSAT is compared with a wide set of SOTA parallel SAT solvers on extensive benchmarks including combinatorial and industrial problems. Results show that FastFourierSAT computes the gradient 100+ times faster than previous prototypes on CPU. Moreover, FastFourierSAT solves most instances and demonstrates promising performance on larger-size instances. Yunuo Cen, Zhiwei Zhang 0001, Xuanyao Fong |
AAAI | 1 |
| 2025 | A Pseudo-Boolean Encoding Method for Rectilinear Steiner Arborescence in VLSI RoutingabstractThis paper presents a novel Pseudo-Boolean Optimization (PBO) framework to solve the Rectilinear Steiner Minimum Arborescence (RSMA) problem, with a focus on the All-Quadrant RSMA scenario. Our framework is designed to compute exact solutions efficiently, even in the presence of isothetic rectilinear obstacles. We also introduce a reduction technique that can reduce more than 17% of the encoded variables and constraints to improve solving efficiency. Our method guarantees optimality and offers flexibility and adaptability for large-scale instances. The experimental results indicate that the proposed framework solves 82.3% of 40-point instances and 64.3% of 50-point instances within 300 seconds. Yunuo Cen, Xuanyao Fong |
ISCAS | 2 |
| 2024 | Design Framework for Ising Machines with Bistable Latch-Based Spins and All-to-All Resistive CouplingabstractMemristive crossbars have been proposed as a promising pathway to enabling all-to-all connections for a variety of applications. One such application is the latch-based dynamical Ising machine, which have been proposed for solving combinatorial optimization problems. However, the impact of the design of the memristive crossbar on the performance of the latch-based Ising machine remains unclear. We present a SPICE-level model and simulation framework for analyzing and evaluating the latch-based dynamical Ising machine that use memristive crossbars to achieve all-to-all coupling between Ising spins implemented as latches. Our design space exploration reveals that the solution quality is highly sensitive to the circuit and device design parameters and sizes of the problems. An effective metric that can capture the effect of several design parameters on the statistical results is then proposed to quantify the system functionality. Finally, optimization techniques based on our proposed metric that models the effect of several design parameters on the solution quality of the Ising machine are proposed and demonstrated on MaxCut solving. Our evaluation results on a 128×128 crossbar array-based design show >98% solution quality across a wide range of problem sizes is achievable. Yimin Wang 0001, Yunuo Cen, Xuanyao Fong |
ISCAS | 2 |