Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

Quantum effects resulting from sub-100 nm features in planar, field-effect-controlled semiconductor structures or devices are discussed, and experimental results are compared with calculations. These devices are based on the GaAs-AlGaAs modulation-doped field-effect transistor (MODFET) and include grating-gate lateral surface superlattices. (LSSLs), grid-gate LSSLs, planar-resonant-tunneling field-effect transistors (PRESTFETs), multiple parallel quantum wires (MPQWs), and arrays of quantum dots (QDs). In contrast to conventional, epitaxially grown vertical quantum structures, planar structures offer the opportunity for electron confinement in three, two, and one dimensions and the flexibility of electrical tuning of quantum effects.>