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Raman G. Viswanathan

dblp:317/4954 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › emerging device technologies
alternative device structures		 0.011997
CMOS scaling into the nanometer regime · Proc. IEEE 1997
Integrated circuit design › technology scaling
CMOS scaling		 0.011997
CMOS scaling into the nanometer regime · Proc. IEEE 1997
Integrated circuit design › semiconductor devices
short-channel effects		 0.011997
CMOS scaling into the nanometer regime · Proc. IEEE 1997
Integrated circuit design
low-power circuit design		 0.011997
CMOS scaling into the nanometer regime · Proc. IEEE 1997
YearPublicationVenuePosition
1997 CMOS scaling into the nanometer regime
abstract
Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.
Yuan Taur, Douglas A. Buchanan, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, H.-S. Philip Wong
 Proc. IEEE8