Technology challenges for silicon integrated circuits with a design rule of 0.1 /spl mu/m and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 /spl mu/m currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 /spl mu/m which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 /spl mu/m technology. 0.1 /spl mu/m technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 /spl mu/m are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 /spl mu/m are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 /spl mu/m is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput.

In retrospect, over the past decade and a half, semiconductor memories have been in the stage of youthful growth. A thousand times increase in density and a ten times increase in speed have been recorded. Semiconductor memories have thus been a key element in the revolutionary development of digital electronics. Today, they are undoubtedly entering their age of maturity. Their density limit will be on the order of 100 Mbits per chip, roughly a hundred times the state of the art, and additional speed increase will be less than ten times. Nonetheless, the challenge is still there. Efforts to search for new technology which will actually bring out, in a cost-effective manner, the remaining density and speed potential of semiconductor memories are essential. A thorough investigation is needed to clarify and overcome mechanisms of phenomena which dominate device reliability and degradation. Integrating various data processing, as well as data storing, functions on a chip is the key to adding values to semiconductor memories.