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Jai Arora

dblp:318/0985 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2025
0009-0004-7759-481XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Hardware accelerators and domain-specific architectures · 25% Processor architecture and microarchitecture · 25%
Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 50% Program verification · 38% Programming languages and type systems · 12%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program verification
automated verification
0.912025
TensorRight: Automated Verification of Tensor Graph Rewrites · Proc. ACM Program. Lang. 2025
Electronic design automation › hardware verification and test
hardware verification
0.912025
TAIDL: Tensor Accelerator ISA Definition Language with Auto-generation of Scalable Test Oracles · MICRO 2025
Processor architecture and microarchitecture
instruction set architecture
0.912025
TAIDL: Tensor Accelerator ISA Definition Language with Auto-generation of Scalable Test Oracles · MICRO 2025
Hardware accelerators and domain-specific architectures
tensor accelerator
0.912025
TAIDL: Tensor Accelerator ISA Definition Language with Auto-generation of Scalable Test Oracles · MICRO 2025
Electronic design automation
test oracle generation
0.912025
TAIDL: Tensor Accelerator ISA Definition Language with Auto-generation of Scalable Test Oracles · MICRO 2025
Compilers and program optimization
accelerator compilation
0.312025
TAIDL: Tensor Accelerator ISA Definition Language with Auto-generation of Scalable Test Oracles · MICRO 2025
Programming languages and type systems › language semantics › formal semantics
denotational semantics
0.312025
TensorRight: Automated Verification of Tensor Graph Rewrites · Proc. ACM Program. Lang. 2025

Methods — techniques the papers use, named apart from their topics

scalable test oracles · 1.7auto-generation · 1.7symbolic execution · 0.9bounded rank analysis · 0.9SMT solving · 0.9
YearPublicationVenuePosition
2025 TAIDL: Tensor Accelerator ISA Definition Language with Auto-generation of Scalable Test Oracles
Devansh Jain 0001, Marco Frigo, Jai Arora, Akash Pardeshi, Krut Patel, Charith Mendis
MICRO3
2025 TensorRight: Automated Verification of Tensor Graph Rewrites
abstract
Tensor compilers, essential for generating efficient code for deep learning models across various applications, employ tensor graph rewrites as one of the key optimizations. These rewrites optimize tensor computational graphs with the expectation of preserving semantics for tensors of arbitrary rank and size. Despite this expectation, to the best of our knowledge, there does not exist a fully automated verification system to prove the soundness of these rewrites for tensors of arbitrary rank and size. Previous works, while successful in verifying rewrites with tensors of concrete rank, do not provide guarantees in the unbounded setting. To fill this gap, we introduce T ensor R ight , the first automatic verification system that can verify tensor graph rewrites for input tensors of arbitrary rank and size. We introduce a core language, T ensor R ight DSL, to represent rewrite rules using a novel axis definition, called aggregated-axis , which allows us to reason about an unbounded number of axes. We achieve unbounded verification by proving that there exists a bound on tensor ranks, under which bounded verification of all instances implies the correctness of the rewrite rule in the unbounded setting. We derive an algorithm to compute this rank using the denotational semantics of T ensor R ight DSL. T ensor R ight employs this algorithm to generate a finite number of bounded-verification proof obligations, which are then dispatched to an SMT solver using symbolic execution to automatically verify the correctness of the rewrite rules. We evaluate T ensor R ight ’s verification capabilities by implementing rewrite rules present in XLA ’s algebraic simplifier. The results demonstrate that T ensor R ight can prove the correctness of 115 out of 175 rules in their full generality, while the closest automatic, bounded -verification system can express only 18 of these rules.
Jai Arora, Sirui Lu, Devansh Jain 0001, Tianfan Xu, Farzin Houshmand, Phitchaya Mangpo Phothilimthana, Mohsen Lesani, Praveen Narayanan, Karthik Srinivasa Murthy, Rastislav Bodík, Amit Sabne, Charith Mendis
Proc. ACM Program. Lang.1