Pieter Hijma

dblp:32/10102 · DBLP profile ↗
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8ranked-venue papers
3as first author
3since 2021 · last 2023
0000-0002-5716-1118ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 first-author · 1 since 2021Software engineering, systems software and programming languages · 3 · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1
YearPublicationVenuePosition
2023 Innermost many-sorted term rewriting on GPUs
abstract
This article presents a way to implement many-sorted term rewriting on a GPU. This is done by letting the GPU repeatedly perform a massively parallel evaluation of all subterms. Innermost many-sorted term rewriting is experimentally compared with a relaxed form of innermost many-sorted term rewriting, and two different garbage collection mechanisms, to remove terms that are no longer needed, are discussed and experimentally compared. It is concluded that when the many-sorted term rewrite systems exhibit sufficient internal parallelism, GPU rewriting substantially outperforms the CPU. Both relaxed innermost many-sorted rewriting and garbage collection further improve this performance. Since the implementation can probably be even further optimised, and because in any case GPUs will become much more powerful in the future, this suggests that GPUs are an interesting platform for (many-sorted) term rewriting. As term rewriting can be viewed as a universal programming language, this also opens a route towards programming GPUs by term rewriting, especially for irregular computations.
Johri van Eerd, Jan Friso Groote, Pieter Hijma, Jan Martens 0001, Muhammad Osama 0003, Anton Wijs
Sci. Comput. Program.3
2023 Linear parallel algorithms to compute strong and branching bisimilarity
abstract
Abstract We present the first parallel algorithms that decide strong and branching bisimilarity in linear time. More precisely, if a transition system has n states, m transitions and $$\vert Act \vert $$ | A c t | action labels, we introduce an algorithm that decides strong bisimilarity in $$\mathcal {O}(n+\vert Act \vert )$$ O ( n + | A c t | ) time on $$\max (n,m)$$ max ( n , m ) processors and an algorithm that decides branching bisimilarity in $$\mathcal {O}(n+\vert Act \vert )$$ O ( n + | A c t | ) time using up to $$\max (n^2,m,\vert Act \vert n)$$ max ( n 2 , m , | A c t | n ) processors.
Jan Martens 0001, Jan Friso Groote, Lars B. van den Haak, Pieter Hijma, Anton Wijs
Softw. Syst. Model.4
2022 Lightning: Scaling the GPU Programming Model Beyond a Single GPU
abstract
The GPU programming model is primarily aimed at the development of applications that run one GPU. However, this limits the scalability of GPU code to the capabilities of a single GPU in terms of compute power and memory capacity. To scale GPU applications further, a great engineering effort is typically required: work and data must be divided over multiple GPUs by hand, possibly in multiple nodes, and data must be manually spilled from GPU memory to higher-level memories. We present Lightning: a framework that follows the common GPU programming paradigm but enables scaling to large problems with ease. Lightning supports multi-GPU execution of GPU kernels, even across multiple nodes, and seamlessly spills data to higher-level memories (main memory and disk). Existing CUDA kernels can easily be adapted for use in Lightning, with data access annotations on these kernels allowing Lightning to infer their data requirements and the dependencies between subsequent kernel launches. Lightning efficiently distributes the work/data across GPUs and maximizes efficiency by overlapping scheduling, data movement, and kernel execution when possible. We present the design and implementation of Lightning, as well as experimental results on up to 32 GPUs for eight benchmarks and one real-world application. Evaluation shows excellent performance and scalability, such as a speedup of 57.2 x over the CPU using Lighting with 16 GPUs over 4 nodes and 80 GB of data, far beyond the memory capacity of one GPU.
Stijn Heldens, Pieter Hijma, Ben van Werkhoven, Jason Maassen, Rob van Nieuwpoort
IPDPS2
2020 Rocket: efficient and scalable all-pairs computations on heterogeneous platforms
abstract
All-pairs compute problems apply a user-defined function to each combination of two items of a given data set. Although these problems present an abundance of parallelism, data reuse must be exploited to achieve good performance. Several researchers considered this problem, either resorting to partial replication with static work distribution or dynamic scheduling with full replication. In contrast, we present a solution that relies on hierarchical multi-level software-based caches to maximize data reuse at each level in the distributed memory hierarchy, combined with a divide-and-conquer approach to exploit data locality, hierarchical work-stealing to dynamically balance the workload, and asynchronous processing to maximize resource utilization. We evaluate our solution using three real-world applications, from digital forensics, localization microscopy, and bioinformatics, on different platforms, from desktop machine to a supercomputer. Results shows excellent efficiency and scalability when scaling to 96 GPUs, even obtaining super-linear speedups due to a distributed cache.
Stijn Heldens, Pieter Hijma, Ben van Werkhoven, Jason Maassen, Henri E. Bal, Rob van Nieuwpoort
SC2
2015 An Integrated Approach to Porting Large Scientific Applications to GPUs
abstract
There are many large scientific applications that have been actively developed for several decades. However, in this time the hardware has evolved considerably. It is taking large scientific applications a very long time to get adjusted to the new computing infrastructure. This is because porting these applications to new hardware, such as Graphics Processing Units (GPUs), currently requires a huge amount of manual labor, even though the computations are very well suited for GPUs. In this paper we propose an integrated approach to semi-automatically port large long-lived scientific codes to GPUs. We propose a method that considerably reduces the effort required by experienced GPU programmers to port these applications. This approach is supported by a tool that is able to analyze, transform, and translate source code into different programming languages. We evaluate our approach by applying it to the Parallel Ocean Program, a representative, very large, and widely-used scientific application.
Ben van Werkhoven, Pieter Hijma
e-Science2
2015 Cashmere: Heterogeneous Many-Core Computing
abstract
New generations of many-core hardware become available frequently and are typically attractive extensions for data-centers because of power-consumption and performance benefits. As a result, supercomputers and clusters are becoming heterogeneous and start to contain a variety of many-core devices. Obtaining performance from a homogeneous cluster-computer is already challenging, but achieving it from a heterogeneous cluster is even more demanding. Related work primarily focuses on homogeneous many-core clusters. In this paper we present Cashmere, a programming system for heterogeneous many-core clusters. Cashmere is a tight integration of two existing systems: Satin is a programming system that provides a divide- and-conquer programming model with automatic load-balancing and latency-hiding, while Many-Core Levels is a programming system that provides a powerful methodology to optimize computational kernels for varying types of many-core hardware. We evaluate our system with several classes of applications and show that Cashmere achieves high performance and good scalability. The efficiency of heterogeneous executions is comparable to the homogeneous runs and is >90% in three out of four applications.
Pieter Hijma, Ceriel J. H. Jacobs, Rob van Nieuwpoort, Henri E. Bal
IPDPS1
2015 Stepwise-refinement for performance: a methodology for many-core programming
abstract
Summary Many‐core hardware is targeted specifically at obtaining high performance, but reaching high performance is often challenging because hardware‐specific details have to be taken into account. Although there are many programming systems that try to alleviate many‐core programming, some providing a high‐level language, others providing a low‐level language for control, none of these systems have a clear and systematic methodology as a foundation. In this article, we proposestepwise‐refinement for performance: a novel, clear, and structured methodology for obtaining high performance on many‐cores. We present a system that supports this methodology, offers multiple levels of abstraction to provide programmers a trade‐off between high‐level and low‐level programming, and provides programmers detailed performance feedback. We evaluate our methodology with several widely varying compute kernels on two different many‐core architectures: a Graphical Processing Unit (GPU) and the Xeon Phi. We show that our methodology gives insight in the performance, and that in almost all cases, we gain a substantial performance improvement using our methodology. Copyright © 2015 John Wiley & Sons, Ltd.
Pieter Hijma, Rob van Nieuwpoort, Ceriel J. H. Jacobs, Henri E. Bal
Concurr. Comput. Pract. Exp.1
2012 Generating synchronization statements in divide-and-conquer programs
Pieter Hijma, Rob van Nieuwpoort, Ceriel J. H. Jacobs, Henri E. Bal
Parallel Comput.1