A methodology, called Subsystem Access Time (SAT) modeling, is proposed for the performance modeling and analysis of shared-bus multiprocessors. The methodology is subsystem-oriented because it is based on a Subsystem Access Time Per Instruction (SATPI) concept, in which we treat major components other than processors (e.g., off-chip cache, bus, memory, I/O) as subsystems and model for each of them the mean access time per instruction from each processor. The SAT modeling methodology is derived from the Customized Mean Value Analysis (CMVA) technique, which is request-oriented in the sense that it models the weighted total mean delay for each type of request processed in the subsystems. The subsystem-oriented view of the proposed methodology facilitates divide-and-conquer modeling and bottleneck analysis, which is rarely addressed previously. These distinguishing features lead to a simple, general, and systematic approach to the analytical modeling and analysis of complex multiprocessor systems. To illustrate the key ideas and features that are different from CMVA, an example performance model of a particular shared-bus multiprocessor architecture is presented. The model is used to conduct performance evaluation for throughput prediction. Thereby, the SATPIs of the subsystems are directly utilized to identify the bottleneck subsystem and find the requests or subsystem components that cause the bottleneck. Furthermore, the SATPIs of the subsystems are employed to explore the impact of several performance influencing factors, including memory latency, number of processors, data bus width, as well as DMA transfer.

Cross point assignment (CPA) for designs of general architecture is a layout problem that has not been well addressed so far. It is done before detailed routing and is to decide for each net the exact crossing locations on the boundaries of global routing cells (GRC's). To complete the CPA for a whole chip, an order of GRC boundaries needs to be decided, then a sequence of single boundary cross point assignment (SBCPA) tasks are performed. In this paper, we present a tool that performs iteratively the CPA process integrated with global rerouting. The CPA process applies a set of heuristic rules for boundary ordering and employs the well-known linear assignment algorithm to solve the SBCPA problem. For the algorithm we develop a novel and comprehensive cost function that can, in addition to minimizing wire length and via count, reduce the effects of horizontal/vertical constraints, and consider globally the wire topologies in a GRC row or column. Moreover, by performing global rerouting based on accurate congestion status after each CPA iteration, the tool can produce, with a well-improved global wire routing, the final CPA result of each GRC. The result can usually be directly input to detailed routing with much higher completion rate and thus can relieve the efforts of post-routing clean up. This tool has been tested on several gate-array and sea-of-gates chips. In particular, the benchmark chips, Primary1 and Primary2 have been successfully routed with about 17% track usage improvement.>

Article Free Access Share on On testing wave pipelined circuits Authors: Jui-Ching Shyur Department od Electrical Engineering, National Taiwan University, Taipei, Taiwan, 10764 R.O.C. Department od Electrical Engineering, National Taiwan University, Taipei, Taiwan, 10764 R.O.C.View Profile , Hung-Pin Chen Department od Electrical Engineering, National Taiwan University, Taipei, Taiwan, 10764 R.O.C. Department od Electrical Engineering, National Taiwan University, Taipei, Taiwan, 10764 R.O.C.View Profile , Tai-Ming Parng Department od Electrical Engineering, National Taiwan University, Taipei, Taiwan, 10764 R.O.C. Department od Electrical Engineering, National Taiwan University, Taipei, Taiwan, 10764 R.O.C.View Profile Authors Info & Claims DAC '94: Proceedings of the 31st annual Design Automation ConferenceJune 1994 Pages 370–374https://doi.org/10.1145/196244.196425Online:06 June 1994Publication History 7citation171DownloadsMetricsTotal Citations7Total Downloads171Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper presents the performance modelling and evaluation of a shared bus multiprocessor, XMP. A key characteristic of XMP is that it employs a special shared bus scheme featuring separate address bus and data bus with split transaction, pipelined cycle (called SSTP scheme). To assist evaluating the architectural alternatives of XMP, the features of the SSTP bus scheme as well as two important performance impacting factors: (1) cache, bus, and memory interferences and (2) DMA transfer, are modelled. We employ a Subsystem Access Time (SAT) modelling methodology. It is based on a Subsystem Access Time Per Instruction (SATPI) concept, in which we treat major components other than processors (e.g. off-chip cache, bus, memory, I/O) as subsystems and model for each of them the mean access time per instruction from each processor. Validated by statistical simulations, the performance model is fed with a given set of representative workload parameters, and then used to conduct performance evaluation for some initial system design issues. Furthermore, the SATPIs of the subsystems are directly utilized to identify the bottleneck subsystems and to help analyze the cause of the bottleneck.

Introduces a formalism, called timed Boolean calculus (TBC), and its applications to solving the false path problem in timing analysis. TBC is an extension of conventional Boolean algebra with a delay operator to facilitate modeling the timing behavior of logic circuits. By performing algebraic manipulations on timed Boolean expressions, the actual maximal delays of logic circuits can be obtained. The delay information can then be used by a path reporting algorithm to detect the long false paths, thereby identifying the paths which need be optimized to meet timing constraints. The authors have developed a timing analysis tool based on TBC and tested on ISCAS benchmarks. Experimental results are shown to justify the effectiveness and efficiency of the proposed TBC and algorithms.>

In this paper we present a new approach to solving the false path problem.

A novel approach to solving the false path problem is proposed. The approach is based on an extended Boolean algebra and is capable of modeling the logic and timing behavior of logic networks in terms of modified Boolean functions. By applying algebraic manipulations, one can use this approach to extract correct timing information such as path delays as well as the input vectors to activate the sensitizable paths. There are two innovative ideas involved in the approach: (1) an algebraic method is used to deal with the problem of delay analysis, and (2) the rising and falling delays of each node are extracted separately. The approach has been implemented and tested on ISCAS benchmarks.>

The authors integrate the concepts and techniques of two existing complementary approaches, namely, the rerouting approach and the top-down hierarchical approach based on linear assignment. This combines and enhances the advantages of the two approaches and results in a fast and high-quality router which can handle large sea-of-gates designs. In addition, it solves the problems of routing interdependence and routing resource estimation which heretofore have not been well addressed yet. The method has been implemented and successfully tested on three real gate-arrays chips: Primary 1, Primary 2, and a channelless industrial example with 100 K gates.>