The verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the circuit highly depends on the timed behavior of its components and the environment. To verify the system, three techniques have been combined: (1) relative-timing-based verification from absolute timing information, (2) assume-guarantee reasoning to verify untimed abstractions of timed components and (3) mathematical induction to verify pipelines of any length. Even though the circuit can interact with pulse-driven environments, the internal behavior between stages commits a handshake protocol that enables the use of untimed abstractions. The verification not only reports a positive answer about the correctness of the system, but also gives a set of sufficient relative-timing constraints that determine delay slacks under which correctness can be maintained.

This paper presents a novel approach for automatic test patterngeneration of asynchronous circuits. The techniques used for thispurpose assume that the circuit can only be exercised by applyingsynchronous test vectors, as is done by real-life testers.The main contribution of the paper is the abstraction of thecircuit's behavior as a synchronous finite state machine in such away that similar techniques to those currently used for synchronouscircuits can be safely applied for testing.Currently, the fault model being used is the input stuck-at model.Experimental results on different benchmarks show that our approachgenerates test vectors with high fault coverage.

This paper presents a novel technique for synthesis of speed-independentcircuits. It is based on partial order representation ofthe state graph called STG-unfolding segment. The new methoduses approximation technique to speed up the synthesis process.The method is illustrated on the basic implementation architecture.Experimental results demonstrating its efficiency are presented anddiscussed.