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Anh Dinh

dblp:32/3610 · DBLP profile ↗
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5ranked-venue papers
1as first author
3since 2021 · last 2026
0000-0002-2625-547XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorArtificial intelligence and machine learning · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Distributed systems · 100%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computing education · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computing education › AI education
AI literacy
1.012026
Catching the First Light of Tomorrow: A Hackathon-Based Framework for Introducing High School Students to AI Agents · AAAI 2026
Distributed systems › consistency models
causal ordering
0.912025
FairDAG: Consensus Fairness over Multi-Proposer Causal Design · Proc. VLDB Endow. 2025
Distributed systems
consensus
0.912025
FairDAG: Consensus Fairness over Multi-Proposer Causal Design · Proc. VLDB Endow. 2025
Computing education › k-12 education
k-12 computing education
0.312026
Catching the First Light of Tomorrow: A Hackathon-Based Framework for Introducing High School Students to AI Agents · AAAI 2026

Methods — techniques the papers use, named apart from their topics

prompt engineering · 1.0large language model · 1.0
YearPublicationVenuePosition
2026 Catching the First Light of Tomorrow: A Hackathon-Based Framework for Introducing High School Students to AI Agents
abstract
Artificial Intelligence (AI), particularly in the form of intelligent AI agents, is transforming education, industry, and everyday life. These agents extend the capabilities of Large Language Models (LLMs) by integrating planning, decision-making, tool use, and multi-agent collaboration, enabling systems that can reason, adapt, and act in dynamic environments. As such systems become integral to modern workplaces and everyday problem solving, early exposure equips high school students with systems thinking, practical problem-solving skills, and ethical awareness, while preparing them to create applications that address real-world needs. Yet most high school AI programs focus on basic model usage and overlook the skills required to design and deploy agentic systems. Existing resources are largely aimed at university learners and assume substantial programming expertise, creating a significant accessibility gap. To address this need, we present a structured hackathon-based framework for introducing high school students to the design and application of AI agents. The framework combines expert-led lectures on core topics such as agent architectures, prompting strategies, reasoning methods, and tool-use protocols with a guided hackathon in which students collaboratively develop domain-specific agent-based chatbots. We provide a complete suite of instructional materials, step-by-step tutorials, and starter code to support hands-on learning, enabling participants to build functional agents capable of reasoning and interacting with external tools. Our approach bridges the gap between AI literacy and practical deployment while fostering creativity, collaboration, and responsible innovation, and our findings suggest that early engagement with agent-based AI design equips students with both technical proficiency and the mindset to shape the AI-driven future.
Long S. T. Nguyen, Quan Bui, Dung Phan, Dung Le, Khang Vo, Nam Duong, Anh Dinh, Tri Trinh, Chi Phan, Thai Nguyen, Dang Le, Vinh Dang, Thanh Tho Quan
AAAI10
2025 FairDAG: Consensus Fairness over Multi-Proposer Causal Design
Dakai Kang, Junchao Chen 0003, Anh Dinh, Mohammad Sadoghi
Proc. VLDB Endow.3
2022 Fetal ECG Extraction From Maternal ECG Using Attention-Based CycleGAN
abstract
A non-invasive fetal electrocardiogram (FECG) is used to monitor the electrical pulse of the fetal heart. Decomposing the FECG signal from the maternal ECG (MECG) is a blind source separation problem, which is hard due to the low amplitude of the FECG, the overlap of R waves, and the potential exposure to noise from different sources. Traditional decomposition techniques, such as adaptive filters, require tuning, alignment, or pre-configuration, such as modeling the noise or desired signal to map the MECG to the FECG. The high correlation between maternal and fetal ECG fragments decreases the performance of convolution layers. Therefore, the masking region of interest based on the attention mechanism was performed to improve the signal generators' precision. The sine activation function was also used to retain more details when converting two signal domains. Three available datasets from the Physionet, including the A&D FECG, NI-FECG, and NI-FECG challenge, and one synthetic dataset using FECGSYN toolbox, were used to evaluate the performance. The proposed method could map an abdominal MECG to a scalp FECG with an average of 98% R-Square [CI 95%: 97%, 99%] as the goodness of fit on the A&D FECG dataset. Moreover, it achieved 99.7% F1-score [CI 95%: 97.8-99.9], 99.6% F1-score [CI 95%: 98.2%, 99.9%] and 99.3% F1-score [CI 95%: 95.3%, 99.9%] for fetal QRS detection on the A&D FECG, NI-FECG and NI-FECG challenge datasets, respectively. Also, the distortion was in the "very good" and "good" ranges. These results are comparable to the state-of-the-art results; thus, the proposed algorithm has the potential to be used for high-performance signal-to-signal conversion.
MohammadReza Mohebbian, Seyed Shahim Vedaei, Khan A. Wahid, Anh Dinh, Hamid R. Marateb, Kouhyar Tavakolian
IEEE J. Biomed. Health Informatics4
2010 Low-power low-complexity carrier-based UWB transmitter in 90nm CMOS for wireless biomedical radar sensing applications
abstract
This paper presents a low-power low-complexity ultra-wide band (UWB) transmitter designed in 90nm CMOS technology for UWB radar sensing applications. The proposed design is carrier-based and is targeting for motion detection, biomedical imaging, and short range data communications. This non-coherent UWB transmitter, generates on-off modulated signals at different carrier frequency within the 3-10 GHz band. A voltage controlled oscillator generates a modulated pulse consisting of multiple cycles of sinusoidal waves with smaller bandwidth. The carrier frequency can be adjusted over the whole UWB frequency band by changing the capacitance of a capacitor bank. The transmitter driver controls the output power and matches the 50Ω antenna load. The average power consumption of the transmitter is 1.85mW at a carrier frequency of 9GHz using 1V supply.
Xubo Wang, Anh Dinh, Daniel Teng
ISCAS2
2005 A hardware-efficient technique to implement a trellis code modulation decoder
abstract
This brief presents a new technique in implementing a very large-scale integration trellis code modulation (TCM) decoder. The technique aims to reduce hardware complexity and increase decoding throughput. The technique is introduced in the design of a Viterbi decoder. To simplify the decoding algorithm and calculation, branch cost distances are pre-calculated and stored in a distance look-up table (DLUT). The concept of DLUT significantly reduces hardware requirements as this table eliminates the need for calculation circuitry. In addition, an output LUT (OLUT) is constructed based on the trellis diagram of the code. This table generates the decoding output using information provided by the algorithm. The use of this OLUT reduces the amount of storage requirement. The technique was used to design a 16-state, radix-4 codec for two-dimensional and four-dimensional TCM. The decoder was implemented in hardware after functional simulation. The tested ASIC has a core area of 1.1 mm/sup 2/ in 0.18-/spl mu/m CMOS. A decoding speed of 1 Gbps was achieved. Implementation results have shown that LUTs can be used to decrease hardware requirement and increase decoding speed.
Anh Dinh
IEEE Trans. Very Large Scale Integr. Syst.1