The presented Bandgap Reference (BGR) generator for automotive applications provides both voltage and current references exploiting switched-capacitor techniques to reduce area and power consumption. The BGR is made up of two separate circuits to produce a Proportional-To-Absolute-Temperature (PTAT) current and a Complementary-To-Absolute-Temperature (CTAT) current to be properly summed up on two different branches to provide both voltage and current references. The CTAT current reference generator exploits switched-capacitor circuits, not relying on a high-precision clock generator, to achieve a VBE division and thus reduce both area, by minimizing resistors, and power consumption. A prototype to operate in automotive systems is realized in a 350 nm BCD process with a die area of 0.030 mm2. From a 3V supply it consumes 3 μW, of which the CTAT generator consumes only 1.125 μW. The current reference value provided is 1 μA with a TC of 110 ppm/°C, and the voltage reference value is 125 mV with a TC of 61 ppm/°C from -40°C to 175°C. The robustness of the technique is validated by PVT and Monte Carlo simulations and extended measurements.

This paper presents a methodology based on SystemC-AMS and supported by the COSIDE graphical design environment for the development of automatic test-solutions for Integrated Circuits, which optimises the design of test-hardware and the coding of test-programs.The proposed development framework allows efficient design of test-hardware and rapid mixed-signal simulation of test-program sections, offering insight on the analog behaviour of the test-setup and on the interaction between the test-hardware, the Automatic Test Equipment and the Device Under Test, allowing early investigation and troubleshooting of the test-solution.The framework is validated within an industrial test-scenario by investigating solutions for the measurement of a rapidly changing voltage curve and by designing a narrow current pulse generator circuit where active components are used to modulate the native Automatic Test Equipment capabilities. The investigated solutions are integrated in the physical test-board and probe-card of the specific Device Under Test, and bench measurements are performed within the test-program execution.The comparison between simulation results and bench measurements highlights the capability of the presented SystemC-AMS framework in offering an accurate analog representation of the modelled components and properly supporting the development of automatic test-solutions.

Audio sensors systems scaling leads to microphone interfaces built in deep sub-micron technologies, which introduces critical aspects in high performance analog cells design. In this paper a Cascode Flipped Voltage Follower interface for Micro Electro-Mechanical System (MEMS) silicon microphones is presented. The pseudo-differential interface architecture suits differential microphones, gaining in linearity performance due to symmetry properties of the system. The device is based on the cascode flipped voltage follower, which allows minimizing chip area and power consumption, while enhancing noise and distortion. A prototype in 55nm CMOS features an A-weighted output integrated noise in audio frequency range of −112 dBV(A) and an Acoustic Overload Point (AOP) of$\mathbf{133}\boldsymbol{dB}_{\boldsymbol{spl}}$. Power consumption is lower than$\mathbf{225}\boldsymbol{\mu} \boldsymbol{W}$from a 1.5 V voltage supply.

This paper presents a continuous time voltage amplifier based on a classical MOS Transistor (MOST) input differential stage feeding a regulated cascode output stage. One of the most interesting aspects of the presented circuit is the introduction of complex conjugated poles in the output stage which together with a simple R-C network at the input of the differential stage allows to synthesize a 3rd-order low-pass Butterworth transfer function at 20 dB of passband gain. The proposed circuital technique has been validated by the design of a 3rd-order low-pass filter and amplifier in 28 nm CMOS technology. The proposed circuit has 5.2 nV/√Hz in-band Input Referred Noise (IRN) Power Spectral Density (PSD), −3.2 dBm Input 3rd-order Intercept Point (IIP3) at 20 dB passband gain and a final Signal-to-Noise-Ratio (SNR) of 60 dB. This solution is particularly efficient in terms of both power consumption and linearity while performing large SNR, as demonstrated by the final Figure-of-Merit of 159.2 dBJ−1.

In recent car developments, the proliferation of Communication systems with several electronics nodes results in increased cost, complexity, and wire harness weight. Such nodes are usually connected by several wires, like a differential communication bus, power supply lines, and possibly addressing lines. In this paper, novel transmitter designs for reducing the amount of interconnects between the nodes are proposed, exploting communication on the power lines, occupying unused parts of the spectrum. Besides the cost-saving, such methods reduce the automotive harness complexity and lead to more flexible solutions, lowering the demand for raw material and consequently reduced emissions during the production process. However, this requires adding specific sections to apply communication to the power line in each IC devices controlling the nodes. In this paper, some 180nm HV-CMOS SOI transmitter solutions are proposed to operate a data rate of up to 2Mbps. Extended simulations in an automotive environment model validate and compare the proposals.

This paper presents the design and experimental characterization of a Proton Sound Detector (ProSD), a device that physically captures and senses the weak acoustic signal emitted by the fast energy deposition at the end of the same proton beam range. The measured acoustic signal Time-of-Flight provides a very accurate (13 μm accuracy) measure of the proton beam penetration depth in water, improving the proton range verification accuracy w.r.t. previous works in pre-clinical scenarios. This suggests interesting possibilities for high-accuracy and real-time beam monitoring and calibration in hadron-therapy for cancer treatment. The detector has been fully characterized and tested with a physical 20 MeV proton beam in a water energy absorber. The ProSD and the water tank have been mounted in front of the exit layer of a 20 MeV 120 ns pulse time-width proton beam. A clear sinusoidal-like acoustic signal of 5 Pa and 2.3 MHz frequency has been detected at 12 dB SNR with 0.8 Gy single shot dose. After averaging 10 beam shots the achieved Signal-to-Noise-Ratio is 22 dB allowing a ±7.5 μm precision vs. previously reported ±45μm ionoacoustic precision.

The synergy between schematic and layout to optimize the performance of analog circuits in scaled technologies is addressed for the case of an innovative analog filter, developed in the 28nm node. This benchmark is a 75MHz 4th-order low-pass analog filter in 28nm-CMOS composed by two Active-RC Rauch biquadratic cells. The architecture is customized to properly operate in the challenging conditions of low VDD(0.9V) and low [VDD-VTH] space (≈ 0.4V) and overcoming the poor analog performance of the 28nm MOS devices. In these directions, aggressive opamp input and output CMFB are applied. The paper shows how layout could corrupt the high-frequency performance of the filter without specific solutions. Optimized and synergic design and layout solutions are validated by the experimental results. The filter consumes 2.68mW from a single 0.9V-VDD. 11.5dB IIP3 at 20&21MHz and 40dBc of THD at 20MHz, respectively are achieved, while performing 310µVRMSof integrated in band noise.

In this paper a 75MHz 4thorder low-pass analog filter in CMOS-28nm is presented. The filter is composed by the cascade of two Active-RC Rauch biquadratic cells. The hereby proposed design manages a very low Vdd/Vth ratio (<;2) for Standard-Process (SP) MOS transistors by means of a dedicated input Common-Mode (CM) feedback circuit (I-CMFB), that operates the OPAMP input differential pair in weak inversion region independently on common mode variations. The single Rauch cell exploits a feed-forward compensated OPAMP, where an improved output CM feedback (O-CMFB) circuit has been adopted reducing this way the parasitic poles of the CM loop, and improving O-CMFB phase margin. The OPAMP has been designed using a folded topology for stable operating point. The design prototype achieves 75MHz-3dB frequency at 2.8mW power consumption from a single 0.9V supply voltage, including also I-CMFB and O-CMFB power. In-band integrated noise is 320uVrms. The filter performs 20dBm and 13dBm IIP3 at 6&11MHz and 50&55&MHz, respectively. Thanks to the very large linearity achieved at edge of the signal pass-band this design has one of the highest Figure-of-Merit for Active-RC filters.

This paper presents the design of a 4th-order closed-loop continuous-time filter. This filter exploits an improved analog stage that makes linearity performance constant over the entire pass-band frequencies. In other words the filter has same IIP3 at low and at high frequency. Hence the linearity performance are independent on the input tones bandwidth, whereas most of analog filters suffers from poor linearity when loop-gain reduces, i.e. close to the closed-loop poles frequency. In order to validate the hereby proposed design idea a 4th-order 25MHz-3dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28nm technology. The prototype consumes 820μW from 1V supply voltage and has 15dBm and 13dBm IIP3 at 5&6MHz and 20&21MHz input tones, respectively.

A 4th-order 28.8MHz low-pass analog filter uses a modified version of Sallen-Key (SK) biquad that solves the standard SK cell critical aspect due to the out-of-band zeros (OoB). The proposed cell completely cancel the OoB zeros by means of a low-power auxiliary path and a specific design optimization.

This paper presents a 4th-order low-pass continuous-time filter with 21.4 MHz bandwidth. Using a positivefeedback in combination with resistors, this architecture synthesizes two complex conjugate poles. The filter is designed and optimized to feature high-linearity along all filter passband, and, in particular, at the cut-off frequency edge. The filter consumes only 100 μA with 1.8V voltage supply, and achieves 45μW/pole power consumption, 300 μVRMSinput-referred noise, 21.9 dBm IIP3 with 2–3 MHz input tones and 12dBm IIP3 near the cut frequency using 19–20 MHz tones.

This paper presents an FSK modulator suitable for a transmitter chain within the new USB Power Delivery standard. The proposed solution performs a binary FSK modulation using a relaxation voltage-controlled oscillator with a voltage averaging feedback. A reference proportional to supply is used to compensate real-time frequency variations, whereas the frequency spread due to the process is corrected by an 8 bit trimming system. The considered input signal bit rate is 300 kbps and the carrier frequency is 23.2 MHz with ±0.5 MHz frequency deviation. The proposed modulator grants ±0.9% accuracy against PVT spread by consuming 1.2 mW and phase noise at 20kHz from the carrier lower than -56 dBc/Hz.

This paper presents GEMINI, an entire read-out System-on-Chip (SoC) to be used with the Triple Gas-Electron Multiplier (GEM) detector. Designed in CMOS 180 nm technology, GEMINI pushes towards the state-of-the-art for this peculiar detector front-end, as regards the count rate and detector pixel parasitic capacitance sustainability. It is composed of 16 channels, each performing a charge-to-voltage conversion via a Charge-Sensitive Preamplifier (CSP), a successive event discrimination with channel-independent threshold and an event-triggered reset. The CSP analog output and the LVDS discriminator output are available as chip outputs for each channel. The Q-to-V conversion accuracy is guaranteed by an automatic on-chip calibration unit, compensating for environmental, CMOS process and supply voltage variations. GEMINI is able to sustain a 5 Mcps count rate, managing up to 40 pF pixel capacitance and with a 2.7mW/ch power consumption.

An efficient algorithm for a link budget definition of a Bluetooth Low Energy (BLE) receiver is presented. The aim of this paper is to provide a simple procedure that the analog designers can use for a preliminary but reliable definition of the BLE RX building blocks specs. Starting from the BLE standard, the global specifications of the analog front-end are derived (noise figure, IIP3, IIP2, etc.) and, in a second phase, distributed among the building blocks. Finally the system design is validated through simulation results obtained from a Simulink analysis.

In this paper a highly linear-dual band RF front-end (LNA and Mixer) for IR-UWB (IEEE 802.15.4a) applications is proposed. LNA exploits a common-gate (CG) stage in parallel to a common-source (CS). It performs single-ended to differential-ended operation, avoiding balun stage. It features 18 dB maximum gain,+11.8 dBm IIP3. The RF front-end receiver has been designed in 65nm CMOS technology consuming 13.5 mW.

The design of an automatic biasing system for High-Electron-Mobility-Transistors is here presented (HEMT-Biasing-System, HBS). The HBS automatically regulates the operating point of an off-chip multistage HEMT block. A proper automatic algorithm is implemented in order to maximize the HEMT transconductance (gm) efficiency (defined as gm/IDSratio). This is an important feature in several HEMT-based systems, since they are used in LNA stages, where noise/power trade-off is a key aspect. Interfacing CMOS and HEMT technologies features several design issues, like negative gate-source voltage (to be managed by a CMOS circuits for HEMT switch-off operation) and closed-loop stability (due to the presence of very large off-chip capacitance - 100nF). The System here presented manages all these issues with tailored circuit solutions. A prototype has been designed in CMOS 0.35μm technology. It consumes 6.2mW (excluding the current consumption for HEMT driving).

In this paper a 5thorder low-pass continuous time analog filter in CMOS 45nm technology is presented. The filter design is based on a single compact cell used to synthesize five poles. The circuit performs the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 1-GHz -3dB-bandwidth is obtained by a prototype of the filter simulated in 45nm CMOS technology node (also Process-Voltage-Temperature simulations are available). The overall power consumption is 9mW from a single 1.2V supply voltage. 54dB@THD>40dBc is the SNR at 0dB gain.

In this paper the complete design of a Programmable Gain Amplifier embedded in UWB receiver is presented. The receiver is part of a System-On-Chip placed inside the car tire (with the aim to interchange data with the car control unit) where dynamic stress, temperature and aging are very important issues, resulting in severe design constraints for CMOS analog integrated circuits. Furthermore, the SoC is biased by vibration-based energy scavenger, and a as consequence, very low power is available for the integrated circuits. High input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/vHz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.

In this paper a low-cost integrated wide-range gas sensor interface based on a resistance-to-time converter is presented. The circuit in transistor level simulation achieves a linearity better than 0.5% over a range of 6 decades i. e. 1 kΩ ÷ 1 GΩ, without requiring any calibration or auto-ranging. The maximum sensing time is 0.5 s, while measuring the highest resistance value. The state-of-the-art of this measurement has been improved by extending the acceptable input resistance range, while lowering the maximum power consumption. More over, a very high linearity has been achieved by canceling the parasitic effects of the multiplexer addressing the sensor matrix.

In this paper a 11MHz-f@-3dBcontinuous-time analog filter is presented. A low-noise circuital topology has been used based on typical Active-RC cells, like opamp-based integrators, and Active-Gm-RC biquadratic cell. The basic idea is to synthesize two complex poles pairs (4th-Order Filter) using a single compact Active RC cell, which minimizes the in-band noise power contributions. A filter prototype, complying with WLAN baseband requirements, has been designed in CMOS 90nm technology. Thanks to noise power spectral density reduction - 48μVrmsoutput integrated noise (100kHz÷11MHz) at 0dB-pass-band gain - wide Dynamic Range (84dB@THD>;40dBc) is performed. In-band IIP3 is 10dBm, while the filter power consumption is 14mW.

This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2chip area.

This paper presents a digital amplitude modulator (DAM) for polar transmitter in 90 nm CMOS technology. It consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB error vector magnitudes (EVM) and 18% drain efficiency. The 8-bit are segmented addressed. This results in a very compact 0.007 mm2chip area.

In this paper the design of a 10b 100-MS/s pipeline analog-to-digital converter (ADC) with an optimized bit-stage resolution is presented. A careful analysis of the ADC architecture is presented. The proposed architecture is made by two main stages with opamp-sharing technique and a 3b full-flash ADC. The 1ststage has a 1.5b resolution architecture, the remaining stages have 2.5 b resolution architecture. Furthermore, the input sampling is directly performed on the 1ststage. The ADC is implemented in 65 nm digital CMOS process technology. It achieves 69.3 dB spurious-free-dynamic-range (SFDR), 59.3 dB signal-to-noise ratio (SNR), 9.6 effective number of bits (ENOB) for a 49 MHz input at full sampling rate. The ADC power consumption is about 12.7 mW from a 1.2 V supply. The FOM value is about 165 fJ/conv. It occupies 0.8mm2.

In this paper we present a 1.6-GHz pipeline A/D converter (ADC) for digital television and digital broadcast satellite. The ADC, designed in a standard 65-nm CMOS technology, achieves in simulation a signal-to-noise and distortion ratio (SNDR) of 54.3 dB (8.73 ENOB), over a signal bandwidth of 615 MHz. The ADC core consumes 430 mW from 1-V and 2.5-V power supplies. In order to achieve the required sampling frequency, the proposed ADC exploits a time-interleaved architecture with four paths. Each path consists of a 10-bit pipeline ADC with four stages (a 3.5-bit stage, a 1.5-bit stage, a 2.5-bit stage and a final 4-bit flash stage). Operational amplifier sharing is adopted in the last two stages for reducing the power consumption. The active area of the chip is 2.7 × 3.2 mm2.

In this paper two different design approaches for a large tuning range LP filter for DVB-T receivers are presented. The LP filter is placed at the beginning of the receiver chain, before to the RF and base band blocks, so that the design is challenging because high out-band frequencies rejection is required while maintaining low input referred noise. Closed-loop topologies have been investigated to comply with the in-band linearity requirements. A system level analysis has been developed using a proper Matlab procedure. This procedure allows optimizing the basic filter parameters - opamp bandwidth, R and C values - in order to satisfy the filter transfer function requirements. Two different design approaches will be considered. The first proposal is based on a 2nd order biquadratic cell. High quality factor is synthesized while guaranteeing the out-of-band frequencies rejection. The second implementation is based on the cascade of two biquadratic cells with more relaxed quality factor requirement. The design is realized using the 90nm CMOS technology. The simulation results for both implementations are presented. The minimum out-of-band rejection is maintained lower than -30dB, the maximum IRN in both cases is 4nV/radicHz and the IM3 is lower than -30dB for two in-band input tones.

We report here the results of some laboratory experiments performed to validate the effectiveness of a technique for the self tuning of integrated continuous-time, high-speed active filters. The tuning algorithm is based on the application of a pseudo-random input sequence of rectangular pulses to the device to be tuned and on the evaluation of a few samples of the input-output cross-correlation function which constitute the filter signature. The key advantages of this technique are the ease of the input test pattern generation and the simplicity of the output circuitry which consists of a digital cross-correlator. The technique allows achieving a tuning error mainly dominated by the value of the elementary capacitors employed in the tuning circuitry. The time required to perform the tuning is kept within a few microseconds. This appears particularly interesting for applications to telecommunication multi-standard terminals. The experiments regarding the application of the proposed tuning algorithm to a baseband multi-standard filter confirm most of the simulation results and show the robustness of the technique against practical operating conditions and noise

In this paper a 13b incremental A/D converter for High-Linearity sensors read-out applications is described and characterized. The incremental solution is preferred to traditional ΣΔ architectures to simplify the decimator filter topology, which is actually a single bit digital accumulator. This leads to lower area occupancy and power consumption. The input signal, which can be connected either in single-ended or differential mode, is sampled by a resettable SC integrator, followed by a discrete time comparator, which selects the feedback signal. The silicon prototype has been designed in 0.35μm technology with a power supply of 3.3V and consumes 950μW with throughput rate of 120Hz. The measurements results show an ENOB of 12.41 bits. The chip area is 0.22mm2.

In this paper a complete design of an analog 4th order base band filter for WLAN receivers operating at 600mV supply voltage is presented. The design is based on the use of different input and output opamp common mode voltages and on the Input Common Mode Feedback circuit. The ICMFB allows maximizing the overdrive voltages of the opamp input differential pair MOS, guaranteeing the right operating point. The filter is designed using the 0.13μm CMOS technology and features a wide swing performance (DR=68dB@THD=-40dBc when a 800mVpp,differentialsignal is applied at the filter output nodes) and a low power consumption (3.6mW).

A baseband filter synthesizer that takes a behavioural description of the design and produces an efficient transistor level implementation is presented. The tool optimizes the filter at the cascade level, providing the best trade-off between power consumption and dynamic range, and at the cell level, selecting minimum power solutions, through accurate analytical models and an efficient bi-quad topology. Differently from past cascade design techniques based on dynamic range optimization through linear programming, we focus on power minimization while guaranteeing minimum performance levels, given the increasing importance of power savings in hand-held devices. A synthesized filter has been realized in silicon demonstrating the effectiveness of our approach

In this paper an integrated CMOS front-end circuit for a micro-integrated fluxgate magnetometer is proposed. The system is based on excitation block, that feeds the excitation coil of the sensor and a read-out block that sense the voltage of the pick-up coils. To sense the output signal, the second harmonic detection principle has been chosen to achieve a good compromise between power consumption and noise requirements. An integrated low pass Sallen-Key filter has been used to extract the dc signal after the demodulation. The preliminary measurements, performed with a PCB sensor, show a sensitivity of 920 V/T and a linearity error of 6% full scale. The circuit has been realized in a standard 0.35 mum CMOS process. The power consumption is 8 mW @ 3.3V for the excitation and read-out parts and unit and 42 mW @ 5V for the output power stage

This paper presents a reconfigurable analog baseband channel for multistandard receivers. The circuit, consisting of two variable gain amplifiers and a low-pass filter, fulfills the requirements of GSM, WCDMA (UMTS), WLAN (IEEE 802.11a/b/g), and Bluetooth. The gain, bandwidth and power consumption of the circuit are changed through a digital control word depending on the selected standard. Simulation results, including all of the tests prescribed by the different standards, confirm the validity of the proposed solution. The in-band IIP3 evaluated with maximum gain (68dB/39dB) is 5dBm/1dBm for UMTS/WLAN respectively, while the power consumption is 51.7mW/55mW in the two cases

The 4th generation of wireless systems needs low-power integrated transceivers that can be reconfigured in order to satisfy different standard requirements. Standard analog blocks are often not suitable for this step towards the future because of their lack of flexibility. We defined a novel approach to make active-Gm-RC biquadratic cells completely reconfigurable. The biquad provides digitally programmable bandwidth and hence power consumption with a fully customizable cut-off frequencies range. Besides, the noise level can be conveniently modified leading to a further power saving. We exemplified the use of this basic building block in the design of a flexible low-pass filter for a zero-IF transceiver. A 2nd/4th/6th order Butterworth filter was implemented with a continuous cut-off frequency tuning between 330 KHz and 24.6 MHz and with a current consumption range between 0.6mA to 26mA

In this paper an integrated wide-range gas sensor interface based on a resistance-to-number converter is presented. The circuit in transistor level simulations achieves a precision of about 0.5% over a range of 5 decades, i.e. [1kOmega-100MOmega] without requiring any calibration or autoranging, while reconfiguring the circuit and performing a limited calibration, the dynamic range is expected to rise up to 7 decades, e.g. [100Omega-1GOmega]. The presented technique exploits an integrator-based controlled oscillator, whose main time constant is function of the applied resistance value, named Rsens. The state of the art of this measurement method has been improved by separating the oscillator circuit from the sensing device, leading to higher linearity-speed response factor. The maximum conversion time is 5 seconds, when sensing the highest resistance values, i.e. Rsens=100MOmega, while for the lower half-range (Rsensles320kOmega) the conversion time is only 15ms

This paper presents a novel 10-bit pipeline A/D converter for low noise, self-triggered applications. The proposed A/D converter does not require any timing signal (clock) in order to carry out the conversion, assuming that a sampled signal is provided at the input. The circuit basically operates as "combinatorial logic", propagating the partial conversions and the residues through the various stages asynchronously. The presented ADC has been designed in a standard 0.35 mum CMOS technology and the conversion period is lower than 500 ns (i.e. 2 MHz data rate). The power consumption is 39 mW from a 3.3 V power supply. The total chip area without pads is 2.24 mm2

Continuous-time filters are widely used in signal processing but require a tuning system to align their frequency response. Several tuning techniques have been proposed in the literature, which can be grouped in two basic schemes: master-slave and self-calibration arrangements. Here we propose a novel tuning approach which can be applied to both tuning schemes. The tuning algorithm is based on the application of pseudo-random input test pattern signal and on the evaluation of a few samples of the input-output cross-correlation function. The key advantages of the proposed technique are basically the use of a pseudo-random pattern signal which can be generated by a very simple circuit in a small die area and the simple circuitry required to sample the filter output and to perform the cross-correlation operation. Some experimental results of the application of the proposed tuning technique to a benchmark filter are given in order to assess its effectiveness.

A low-power CMOS continuous-time filter is presented. The filter implements a linearization technique which consists of compensating the driver nonlinearity with an opposite load nonlinearity. This results in requiring a lower overdrive to MOS devices and so in power saving. In addition to this the filter features other characteristics which allows one to reduce power consumption. They are: no parasitic poles, no CMFB, no body effect. Finally using digital tuning the performance is optimized for any operation condition. A prototype cell has been designed in a standard 0.5 /spl mu/m CMOS technology. With a pole frequency in the range 13 MHz-83 MHz (Q=1), the cell features a linear range (1%THD) of 400 mVpp from a 3.3 V supply. The parasitic capacitance is kept lower than 20% of the total capacitance. The power consumption in the tuning range varies from 6 mW to 16 mW.

A 4th-order bandpass switched-capacitor (SC) filter to be used as a part of an implantable device has been designed. The power consumption reduction is a key feature of such a system. This has been achieved by using a 1 V supply (SC operation are guaranteed by using the switched-opamp technique). In addition the active devices operate in the subthreshold region. The filter uses a fully differential topology to reduce the clock feedthrough noise and increase the dynamic range. The filter has been designed in a 0.35 /spl mu/m CMOS technology. It operates at 1 kHz sampling frequency and it consumes about 1.2 /spl mu/W.

A 3.3 V CMOS line-driver is presented. The circuit is designed to be used in a serial bus system. The circuit drives a signal in the 1 MHz-16 MHz range on a 75 /spl Omega/ load with amplitude up to 2 V/sub pp/. The proposed line driver achieved a -3 dB bandwidth of about 150 MHz and performs a THD better than 40 dB for a 16 MHz 2 V/sub pp/ sinewave. The circuit is designed in a standard 3.3 V 0.35 /spl mu/m technology. It consumes about 7.5 mW and it occupies a die area of 0.02 mm/sup 2/.

Power consumption is a key point in the design of high-speed switched capacitor (SC) circuits, which allow to efficiently implement a number of analog functions. Among them, SC ΣΔ modulators are very popular for A/D conversion: in this kind of circuits, operational amplifiers are the most consuming cells because of their requirements in terms of DC gain and unity-gain frequency. A new amplifier with 110dB DC gain and a unity-gain frequency of 250MHz is presented. The large power consumption (20mW) makes critical its use in commercial applications: however, combining this cell with a fast adaptive biasing circuit, high performance may be achieved with a reasonable dissipation.

This work examines the practical issues concerning the realization of switched-capacitors video-rate finite-impulse response filters based on standard CMOS technology. The capacitor spread/sensitivity tradeoff is explored for a number of architectural solutions and an architecture suitable to the challenges of the video field is identified. The nonidealities of switches and operational amplifiers, which must be accounted for at video-rate, are analyzed and practical solutions to prevent performance deterioration are proposed. The implementation of a concrete design case is discussed and presented as a demonstration of the technological solutions proposed.

Switched-capacitor technology implemented by 2.4 /spl mu/m CMOS offers considerable reliability/cost advantages. Its limited clock-rate values are the traditional obstacle to its introduction in high frequency applications, such as video. This obstacle can be removed by an architectural scheme broadening the internal clock rate by an integer factor with respect to the input clock rate. The feasibility of this concept is demonstrated by the switched-capacitor realization of a color difference prefilter complying with Recommendation CCIR 601.>

Design considerations regarding the monolithic realization of a high-speed read-out system to be used in future high luminosity colliders such as LHC are presented, System and circuit solution are presented for the first two blocks: the preamplifier and the RC-CR noise shaper. The electronics will be exposed to neutron irradiation and so the required radiation-hard performance is obtained with a design which takes into account the characterisation of the employed bipolar devices before and after neutron radiation,.>

A design approach for realizing high-frequency Gm-C continuous-time filters is proposed and a circuit implementation is presented. The design approach is based on reducing the effects of the finite impedance at each output node by placing a controlled output active load whose value is taken into account in the filter design. The implementation uses a BiCMOS high-efficiency fully-differential transconductor with an all-passive common-mode feedback. Simulation results of a biquadratic low-pass filter with cut-off frequency up to 82 MHz and load capacitance as large as 3pF conclude the paper.>